公开(公告)号：US20170031411A1

公开(公告)日：2017-02-02

申请号：US15292067

申请日：2016-10-12

Applicant: Intel Corporation

Inventor： Ramnarayanan MUTHUKARUPPAN ,  Harish K. KRISHNAMURTHY ,  Mohit VERMA ,  Pradipta PATRA ,  Uday Bhaskar KADALI

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

Abstract translation: 描述了一种装置，包括：第一和第二处理核; 以及PCU，其可操作用于：为所述装置外部的所述离线外调节器产生第一VID，所​​述第一VID导致所述第一处理核心的第一电源; 并产生与第一VID不同的第二VID，第二VID导致用于第二处理核的第二电源。 描述了一种装置，包括：由数字总线控制的多个功率门晶体管，所述多个功率栅晶体管可操作以向处理核提供第一电源，并接收作为输入的第二电源; ADC，用于接收第一电源并产生代表第一电源的数字输出; 以及控制器，用于接收数字输出代表并产生用于控制多个功率门晶体管的数字总线。

公开(公告)号：US20230236996A1

公开(公告)日：2023-07-27

申请号：US18129748

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Ruchir SARASWAT ,  Sriram VENKATESAN ,  Pradeep KARAMCHETI ,  Mohit VERMA

IPC: G06F13/16 ,  G06T1/60 ,  G06F1/26

CPC classification number: G06F13/1668 ,  G06T1/60 ,  G06F1/266

Abstract: Inter-device communication with a pulse-amplitude modulation (PAM) signal can have at least two data eyes with different Vref levels. A physical interface (PHY) can be trained for the PAM signal by training a first data eye separately from the second data eye. The training can include adjusting the first Vref level separately from the second Vref level to center each reference voltage on its respective data eye.