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Patent Agency Ranking
公开(公告)号：US20210407168A1
公开(公告)日：2021-12-30
申请号：US17070095
申请日：2020-10-14
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US20210407039A1
公开(公告)日：2021-12-30
申请号：US16917791
申请日：2020-06-30
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US12243148B2
公开(公告)日：2025-03-04
申请号：US17070095
申请日：2020-10-14
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US12223615B2
公开(公告)日：2025-02-11
申请号：US16917791
申请日：2020-06-30
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
IPC: G06T3/4007 , G06T7/70 , G06T15/06 , G06T17/20
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US20210374249A1
公开(公告)日：2021-12-02
申请号：US16887602
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Bilgiday Yuce , Sayak Ray , Majid Sabbagh , Xueyang Wang , Monodeep Kar , Hareesh Khattri , Jason Fung
Abstract: The present disclosure detects and/or prevents power analysis side-channel attacks without requiring the use of external measurement devices. A first portion of field programmable gate array (FPGA) circuitry is configured to provide emulated hardware device circuitry and a second portion of the FPGA circuitry is configured to provide power monitoring circuitry. The emulated hardware device circuitry and the power monitoring circuitry are coupled to FPGA power distribution network circuitry. The power monitoring circuitry includes time-to-digital converter (TDC) circuitry that includes observation delay buffers to sample a clock propagation delay. Since the voltage supplied to the buffer circuitry affects the propagation delay, the TDC circuitry outputs a binary sequence representative of one or more power delivery parameters to the emulated hardware device circuitry. Analysis circuitry uses the collected data representative of one or more power delivery parameters to determine the susceptibility of the emulated hardware device circuitry to a power analysis side-channel attack.
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