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公开(公告)号：US20190265973A1
公开(公告)日：2019-08-29
申请号：US15903283
申请日：2018-02-23
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Supratim Pal , Ashutosh Garg , Darin M. Starkey , Guei-Yuan Lueh , Jorge E. Parra , Shubh B. Shah , Wei-Yu Chen , Vikranth Vemulapalli , Narsim Krishna , Brent A. Schwartz , Chandra S. Gurram , Wei Pan , Ashwin J. Shivani
Abstract: Methods and apparatus relating to techniques for fusing SIMD processing units. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an instruction set for execution on at least two graphics processing execution units, determine whether the instruction set requires data dependent addressing, and select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20220198735A1
公开(公告)日：2022-06-23
申请号：US17128708
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Krishan Malik , Narsim Krishna , Rajalakshmi Athimoolam , Amit Mishra
Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.
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