公开(公告)号：US09928076B2

公开(公告)日：2018-03-27

申请号：US14498505

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Darin M. Starkey

IPC: G06F13/28 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3887 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/321 ,  G06F9/3851

Abstract: An apparatus and method for a SIMD unstructured branching. For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute instructions; and a branch unit to process unstructured control flow instructions and to maintain a per channel count value for each channel, the branch unit to store instruction pointer tags for the unstructured control flow instructions in a memory and identify the instruction pointer tags using tag addresses, the branch unit to further enable and disable the channels based at least on the per channel count value.

公开(公告)号：US20190265973A1

公开(公告)日：2019-08-29

申请号：US15903283

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Supratim Pal ,  Ashutosh Garg ,  Darin M. Starkey ,  Guei-Yuan Lueh ,  Jorge E. Parra ,  Shubh B. Shah ,  Wei-Yu Chen ,  Vikranth Vemulapalli ,  Narsim Krishna ,  Brent A. Schwartz ,  Chandra S. Gurram ,  Wei Pan ,  Ashwin J. Shivani

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for fusing SIMD processing units. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an instruction set for execution on at least two graphics processing execution units, determine whether the instruction set requires data dependent addressing, and select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing. Other embodiments are also disclosed and claimed.

公开(公告)号：US09983884B2

公开(公告)日：2018-05-29

申请号：US14498561

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Darin M. Starkey ,  Thomas A. Piazza

IPC: G06F9/44 ,  G06F9/40 ,  G06F9/38 ,  G06F9/30 ,  G06F9/45 ,  G06F9/32

CPC classification number: G06F9/3887 ,  G06F8/443 ,  G06F8/452 ,  G06F9/30058 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30076 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/325 ,  G06F9/3842 ,  G06F9/3851

Abstract: An apparatus and method for a SIMD structured branching. For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute instructions; and a branch unit to process control flow instructions and to maintain a per channel count for each channel and a control instruction count for the control flow instructions, the branch unit to enable and disable the channels based at least on the per channel count.

公开(公告)号：US10699362B2

公开(公告)日：2020-06-30

申请号：US15190663

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Pratik J. Ashar ,  Guei-Yuan Ken Lueh ,  Kaiyu Chen ,  Subramaniam Maiyuran ,  Brent A. Schwartz ,  Darin M. Starkey

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/30 ,  G06F9/455

Abstract: Embodiments provide support for divergent control flow in heterogeneous compute operations on a fused execution unit. On embodiment provides for a processing apparatus comprising a fused execution unit including multiple graphics execution units having a common instruction pointer; logic to serialize divergent function calls by the fused execution unit, the logic configured to compare a call target of execution channels within the fused execution unit and create multiple groups of channels, each group of channels associated with a single call target; and wherein the fused execution unit is to execute a first group of channels via a first execution unit and a second group of channels via a second execution unit.

公开(公告)号：US10360654B1

公开(公告)日：2019-07-23

申请号：US15990328

申请日：2018-05-25

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Supratim Pal ,  Jorge E. Parra ,  Chandra S. Gurram ,  Ashwin J. Shivani ,  Ashutosh Garg ,  Brent A. Schwartz ,  Jorge F. Garcia Pabon ,  Darin M. Starkey ,  Shubh B. Shah ,  Guei-Yuan Lueh ,  Kaiyu Chen ,  Konrad Trifunovic ,  Buqi Cheng ,  Weiyu Chen

IPC: G06F9/38 ,  G06F8/41 ,  G06T1/20 ,  G06F9/30 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00

Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware. The compiler can then insert a software scoreboard sync immediate instruction into compiled program code to manage instruction dependencies and prevent data hazards from occurring.

公开(公告)号：US11900502B2

公开(公告)日：2024-02-13

申请号：US17734983

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Chandra S. Gurram ,  Gang Y. Chen ,  Subramaniam Maiyuran ,  Supratim Pal ,  Ashutosh Garg ,  Jorge E. Parra ,  Darin M. Starkey ,  Guei-Yuan Lueh ,  Wei-Yu Chen

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

公开(公告)号：US11321799B2

公开(公告)日：2022-05-03

申请号：US16726659

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Chandra S. Gurram ,  Gang Y. Chen ,  Subramaniam Maiyuran ,  Supratim Pal ,  Ashutosh Garg ,  Jorge E. Parra ,  Darin M. Starkey ,  Guei-Yuan Lueh ,  Wei-Yu Chen

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a software and hardware optimization that manages scenarios where a write operation to a register is less than an entirety of the register. A compiler detects instructions that make partial writes to the same register, groups such instructions, and provides hints to hardware of the partial write. The execution unit combines the output data for grouped instructions and updates the destination register as single write instead of multiple separate partial writes.

公开(公告)号：US10692170B2

公开(公告)日：2020-06-23

申请号：US16437961

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Supratim Pal ,  Jorge E. Parra ,  Chandra S. Gurram ,  Ashwin J. Shivani ,  Ashutosh Garg ,  Brent A. Schwartz ,  Jorge F. Garcia Pabon ,  Darin M. Starkey ,  Shubh B. Shah ,  Guei-Yuan Lueh ,  Kaiyu Chen ,  Konrad Trifunovic ,  Buqi Cheng ,  Weiyu Chen

IPC: G06F9/38 ,  G06F8/41 ,  G06T1/20 ,  G06F9/30 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00

Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware. The compiler can then insert a software scoreboard sync immediate instruction into compiled program code to manage instruction dependencies and prevent data hazards from occurring.

公开(公告)号：US20190362460A1

公开(公告)日：2019-11-28

申请号：US16437961

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Supratim Pal ,  Jorge E. Parra ,  Chandra S. Gurram ,  Ashwin J. Shivani ,  Ashutosh Garg ,  Brent A. Schwartz ,  Jorge F. Garcia Pabon ,  Darin M. Starkey ,  Shubh B. Shah ,  Guei-Yuan Lueh ,  Kaiyu Chen ,  Konrad Trifunovic ,  Buqi Cheng ,  Weiyu Chen

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F8/41

Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware. The compiler can then insert a software scoreboard sync immediate instruction into compiled program code to manage instruction dependencies and prevent data hazards from occurring.

公开(公告)号：US20170372446A1

公开(公告)日：2017-12-28

申请号：US15190663

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Pratik J. Ashar ,  Guei-Yuan Ken Lueh ,  Kaiyu Chen ,  Subramaniam Maiyuran ,  Brent A. Schwartz ,  Darin M. Starkey

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/38

Abstract: Embodiments provide support for divergent control flow in heterogeneous compute operations on a fused execution unit. On embodiment provides for a processing apparatus comprising a fused execution unit including multiple graphics execution units having a common instruction pointer; logic to serialize divergent function calls by the fused execution unit, the logic configured to compare a call target of execution channels within the fused execution unit and create multiple groups of channels, each group of channels associated with a single call target; and wherein the fused execution unit is to execute a first group of channels via a first execution unit and a second group of channels via a second execution unit.