公开(公告)号：US20240111531A1

公开(公告)日：2024-04-04

申请号：US18369082

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Stephen T. PALERMO ,  Srihari MAKINENI ,  Shubha BOMMALINGAIAHNAPALLYA ,  Neelam CHANDWANI ,  Rany T. ELSAYED ,  Udayan MUKHERJEE ,  Lokpraveen MOSUR ,  Adwait PURANDARE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3887

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

公开(公告)号：US20240056159A1

公开(公告)日：2024-02-15

申请号：US18548942

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Thushara HEWAVITHANA ,  Ranjit CAVATUR ,  Neelam CHANDWANI ,  Ziyi LI ,  Bishwarup MONDAL

IPC: H04B7/06 ,  H04B17/336

CPC classification number: H04B7/0695 ,  H04B7/0617 ,  H04B17/336

Abstract: This disclosure relates to apparatuses, systems, and methods for scheduling user equipment (UE) transmissions, and in particular for scheduling UE transmissions in a 5G New Radio system with a split architecture. The scheduler selects a beamforming algorithm for a UE group that includes a first UE and a second UE, where the beamforming algorithm is based on characteristics of the beamforming algorithm and/or the UE group. The scheduler determines an effective SINR for the UE group based on the beamforming algorithm and determines a summed proportion fair metric for the UE group based on the effective SINR for the UE group. The scheduler schedules a transmission for either the first UE or the UE group, based on a proportional fair metric for the first UE and the summed proportional fair metric for the UE group.

公开(公告)号：US20220222194A1

公开(公告)日：2022-07-14

申请号：US17711986

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Neelam CHANDWANI ,  Shridhar BENDI ,  Rajesh VIVEKANANDHAM ,  Rahul PAL ,  Eric J. DAHLEN ,  Antonio J. HASBUN MARIN ,  Chung-Chi WANG ,  Qian LI ,  Hosein NIKOPOUR ,  Sravanthi KOTA VENKATA ,  Rajesh POORNACHANDRAN ,  Udayan MUKHERJEE

IPC: G06F13/40 ,  G06F13/16

Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.