公开(公告)号：US12199098B2

公开(公告)日：2025-01-14

申请号：US17211745

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Cory Weber ,  Stephen M. Cea ,  Leonard C. Pipes ,  Seahee Hwangbo ,  Rishabh Mehandru ,  Patrick Keys ,  Jack Yaung ,  Tzu-Min Ou

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78

Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US11469299B2

公开(公告)日：2022-10-11

申请号：US16146785

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Dax Crum ,  Patrick Keys ,  Tahir Ghani ,  Susmita Ghose ,  Ted Cook, Jr.

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20190333990A1

公开(公告)日：2019-10-31

申请号：US16475031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/78 ,  H01L29/08 ,  H01L21/56 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/66 ,  H01L23/31 ,  H01L27/088

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US20220415708A1

公开(公告)日：2022-12-29

申请号：US17358903

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Tahir Ghani ,  Patrick Keys ,  Aaron Lilak ,  Anand Murthy ,  Cory Weber

IPC: H01L21/768 ,  H01L29/10 ,  H01L27/088 ,  H01L25/07 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.

公开(公告)号：US11527613B2

公开(公告)日：2022-12-13

申请号：US17145114

申请日：2021-01-08

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US20210159312A1

公开(公告)日：2021-05-27

申请号：US17145114

申请日：2021-01-08

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US20230088753A1

公开(公告)日：2023-03-23

申请号：US17482870

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Aaron D. Lilak ,  Patrick Keys ,  Cory Weber ,  Rishabh Mehandru ,  Anand S. Murthy ,  Biswajeet Guha ,  Mohammad Hasan ,  William Hsu ,  Tahir Ghani ,  Chang Wan Han ,  Kihoon Park ,  Sabih Omar

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/74 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

公开(公告)号：US10892326B2

公开(公告)日：2021-01-12

申请号：US16475031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US20230097948A1

公开(公告)日：2023-03-30

申请号：US17485340

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Patrick Keys ,  Aaron Lilak ,  Cory Weber

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.

公开(公告)号：US11495683B2

公开(公告)日：2022-11-08

申请号：US16795473

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sayed Hasan ,  Stephen Cea ,  Anupama Bowonder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.