-
公开(公告)号:US20230097948A1
公开(公告)日:2023-03-30
申请号:US17485340
申请日:2021-09-25
申请人: Intel Corporation
发明人: Rishabh Mehandru , Stephen Cea , Patrick Keys , Aaron Lilak , Cory Weber
IPC分类号: H01L27/088 , H01L29/78 , H01L21/8234 , H01L21/02 , H01L29/66
摘要: Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.
-
公开(公告)号:US11335789B2
公开(公告)日:2022-05-17
申请号:US16142045
申请日:2018-09-26
申请人: Intel Corporation
发明人: Abhishek Sharma , Cory Weber , Van H. Le , Sean Ma
IPC分类号: H01L29/47 , H01L29/66 , H01L29/45 , H01L29/786 , H01L27/108 , H01L27/24 , H01L29/423
摘要: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.
-
公开(公告)号:US20230088753A1
公开(公告)日:2023-03-23
申请号:US17482870
申请日:2021-09-23
申请人: Intel Corporation
发明人: Stephen M. Cea , Aaron D. Lilak , Patrick Keys , Cory Weber , Rishabh Mehandru , Anand S. Murthy , Biswajeet Guha , Mohammad Hasan , William Hsu , Tahir Ghani , Chang Wan Han , Kihoon Park , Sabih Omar
IPC分类号: H01L29/10 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/74 , H01L29/66
摘要: Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.
-
公开(公告)号:US20220415708A1
公开(公告)日:2022-12-29
申请号:US17358903
申请日:2021-06-25
申请人: Intel Corporation
发明人: Rishabh Mehandru , Stephen Cea , Tahir Ghani , Patrick Keys , Aaron Lilak , Anand Murthy , Cory Weber
IPC分类号: H01L21/768 , H01L29/10 , H01L27/088 , H01L25/07 , H01L29/66 , H01L29/78
摘要: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.
-
公开(公告)号:US09076814B2
公开(公告)日:2015-07-07
申请号:US14297847
申请日:2014-06-06
申请人: Intel Corporation
发明人: Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
IPC分类号: H01L29/76 , H01L29/66 , H01L21/265 , H01L29/417 , H01L29/78
CPC分类号: H01L29/7848 , H01L21/26506 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/78 , H01L29/7847 , H01L29/7849
摘要: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
摘要翻译: 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管,该晶体管具有导通沟道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。
-
6.
公开(公告)号:US11342432B2
公开(公告)日:2022-05-24
申请号:US16833184
申请日:2020-03-27
申请人: Intel Corporation
发明人: Aaron D. Lilak , Rishabh Mehandru , Cory Weber , Willy Rachmady , Varun Mishra
IPC分类号: H01L29/423 , H01L21/02 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/165 , H01L29/66 , H01L29/78 , H01L29/786
摘要: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.
-
-
-
-
-