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公开(公告)号：US09766678B2
公开(公告)日：2017-09-19
申请号：US13758897
申请日：2013-02-04
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
CPC classification number: G06F1/32 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/152 , Y02D10/172
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US10990146B2
公开(公告)日：2021-04-27
申请号：US16359810
申请日：2019-03-20
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Pradipta Patra , Gaurav Goel , Uday Bhaskar Kadali
Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
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公开(公告)号：US20170322581A1
公开(公告)日：2017-11-09
申请号：US15595781
申请日：2017-05-15
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Nandan Chepuri
IPC: G05F3/02
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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公开(公告)号：US11068006B2
公开(公告)日：2021-07-20
申请号：US16377042
申请日：2019-04-05
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Chepuri
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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公开(公告)号：US20190235557A1
公开(公告)日：2019-08-01
申请号：US16377042
申请日：2019-04-05
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Chepuri
IPC: G05F3/02
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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Patent Agency Ranking
公开(公告)号：US10185382B2
公开(公告)日：2019-01-22
申请号：US15292067
申请日：2016-10-12
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US10345881B2
公开(公告)日：2019-07-09
申请号：US15653764
申请日：2017-07-19
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
IPC: G06F9/00 , G06F1/32 , G06F1/3234 , G06F1/3296 , G06F1/324
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US10268249B2
公开(公告)日：2019-04-23
申请号：US15025871
申请日：2013-12-18
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Pradipta Patra , Gaurav Goel , Uday Bhaskar Kadali
Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
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公开(公告)号：US09651978B2
公开(公告)日：2017-05-16
申请号：US14689600
申请日：2015-04-17
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Nandan Chepuri
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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公开(公告)号：US20160306374A1
公开(公告)日：2016-10-20
申请号：US14689600
申请日：2015-04-17
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Nandan Chepuri
IPC: G05F3/02 , H03K17/687
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
Abstract translation: 描述了用于电力管理的装置和方法。 该装置可以包括包括多个电流源的电源门。 电源门可以耦合到负载。 该装置还可以包括耦合到功率门的电压控制电路，以确定并选择多个电流源中的一个或多个电流源来提供给负载。 该装置还可以包括耦合到电压控制电路的电流控制电路，以控制一个或多个电流源的各个电流源以输出恒定电流。 可以描述和/或要求保护其他实施例。
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