公开(公告)号：US20250112198A1

公开(公告)日：2025-04-03

申请号：US18375248

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyasha Mohapatra ,  Kyle Davidson ,  Brian Franco

IPC: H01L23/00

Abstract: An apparatus is provided which comprises: a device surface, wherein the device surface comprises an array of solder contacts, a substrate surface, wherein the substrate surface comprises an array of pads, the array of solder contacts coupled with the array of pads, and a formation of epoxy coupled with the device surface and the substrate surface, wherein the formation of epoxy is entirely within an area of the array of solder contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250112163A1

公开(公告)日：2025-04-03

申请号：US18375203

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Pratyasha Mohapatra ,  Srinivas Pietambaram ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Yosef Kornbluth ,  Kuang Liu ,  Astitva Tripathi ,  Yuqin Li ,  Rengarajan Shanmugam ,  Xing Sun ,  Brian Balch ,  Darko Grujicic ,  Jieying Kong ,  Nicholas Haehn ,  Jacob Vehonsky ,  Mitchell Page ,  Vincent Obiozo Eze ,  Daniel Wandera ,  Sameer Paital ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L25/065

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.