公开(公告)号：US20240243099A1

公开(公告)日：2024-07-18

申请号：US18615654

申请日：2024-03-25

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20210074695A1

公开(公告)日：2021-03-11

申请号：US16646460

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Glenn J. HINTON ,  Rajesh KUMAR

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US20200258852A1

公开(公告)日：2020-08-13

申请号：US16635536

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Doug INGERLY ,  Rajesh KUMAR ,  Harish KRISHNAMURTHY ,  Nachiket Venkappayya DESAI

IPC: H01L23/64 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US20240038722A1

公开(公告)日：2024-02-01

申请号：US18378978

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20220271022A1

公开(公告)日：2022-08-25

申请号：US17742205

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Glenn J. HINTON ,  Rajesh KUMAR

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US20220139896A1

公开(公告)日：2022-05-05

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark T. BOHR ,  Rajesh KUMAR ,  Robert L. SANKMAN ,  Ravindranath V. MAHAJAN ,  Wesley D. MC CULLOUGH

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/498

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US20220302051A1

公开(公告)日：2022-09-22

申请号：US17836117

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark BOHR ,  Doug INGERLY ,  Rajesh KUMAR ,  Harish KRISHNAMURTHY ,  Nachiket Venkappayya DESAI

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

公开(公告)号：US20210225808A1

公开(公告)日：2021-07-22

申请号：US17226967

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20230238357A1

公开(公告)日：2023-07-27

申请号：US18128958

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20200066679A1

公开(公告)日：2020-02-27

申请号：US16348448

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.