公开(公告)号：US20230209759A1

公开(公告)日：2023-06-29

申请号：US18112953

申请日：2023-02-22

申请人： Intel Corporation

发明人： Karumbu MEYYAPPAN ,  Kyle ARRINGTON ,  David CRAIG ,  Pooya TADAYON

IPC分类号： H05K7/14 ,  H05K7/20 ,  H01L23/22

CPC分类号： H05K7/1481 ,  H05K7/20272 ,  H01L23/22

摘要： Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

公开(公告)号：US20210351106A1

公开(公告)日：2021-11-11

申请号：US16871424

申请日：2020-05-11

申请人： Intel Corporation

发明人： Prabhakar SUBRAHMANYAM ,  Tewodros WONDIMU ,  Ying-Feng PANG ,  Muhammad AHMAD ,  Paul DIGLIO ,  David SHIA ,  Pooya TADAYON

IPC分类号： H01L23/427 ,  G01R31/26 ,  B05B1/14

摘要： Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate.

公开(公告)号：US20210225808A1

公开(公告)日：2021-07-22

申请号：US17226967

申请日：2021-04-09

申请人： Intel Corporation

发明人： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20210120703A1

公开(公告)日：2021-04-22

申请号：US17134368

申请日：2020-12-26

申请人： Intel Corporation

发明人： Prabhakar SUBRAHMANYAM ,  Arun KRISHNAMOORTHY ,  Victor POLYANKO ,  Ying-Feng PANG ,  Yi XIA ,  Pooya TADAYON ,  Muhammad AHMAD ,  Rahima K. MOHAMMED

IPC分类号： H05K7/20

摘要： An apparatus is described. The apparatus includes a liquid cooling system having multiple heat-exchangers and multiple valves. The multiple valves are to enable/disable participation of individual ones of the heat-exchangers within the liquid cooling system. The apparatus includes an information keeping device to store information that correlates a number of the multiple heat exchangers to be enabled to realize one or more semiconductor chips' target temperature for a power consumption of the one or more semiconductor chips for a plurality of combinations of target temperature and power consumption. The controller is coupled to the liquid cooling system and the information keeping device to dynamically determine during runtime of a system having the one or more semiconductor chips an appropriate number of the multiple heat exchangers to enable to realize a particular target temperature for the one or more semiconductor chips for a particular power consumption of the one or more semiconductor chips, and, update the information in the information keeping device with a new correlation that correlates the appropriate number with the particular target temperature and particular power consumption

公开(公告)号：US20230238357A1

公开(公告)日：2023-07-27

申请号：US18128958

申请日：2023-03-30

申请人： Intel Corporation

发明人： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20230140685A1

公开(公告)日：2023-05-04

申请号：US18089537

申请日：2022-12-27

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20230091050A1

公开(公告)日：2023-03-23

申请号：US17479031

申请日：2021-09-20

申请人： Intel Corporation

发明人： Zhichao ZHANG ,  Pooya TADAYON ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Changhua LIU ,  Kemal AYGÜN

IPC分类号： G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to optical interconnects and optical waveguides within a glass layer of a semiconductor package, where dies that are physically and optically coupled with the glass layer are optically coupled with each other via the optical waveguides. One or more reflectors may be used to direct the optical pathway through the glass layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210035951A1

公开(公告)日：2021-02-04

申请号：US16524743

申请日：2019-07-29

申请人： Intel Corporation

发明人： Pooya TADAYON

IPC分类号： H01L25/065 ,  H01L23/13 ,  H01L23/538

摘要： Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

公开(公告)号：US20200066679A1

公开(公告)日：2020-02-27

申请号：US16348448

申请日：2017-12-21

申请人： Intel Corporation

发明人： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20240234245A1

公开(公告)日：2024-07-11

申请号：US18612949

申请日：2024-03-21

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/522 ,  H01L23/538 ,  H01L25/07

CPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.