公开(公告)号：US20220413915A1

公开(公告)日：2022-12-29

申请号：US17929577

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Raju Arvind ,  Anil Keshavamurthy ,  Greeshma Pisharody ,  Masoud Sajadieh ,  Mukund Shenoy ,  Ranganath Sunku

IPC: G06F9/50

Abstract: Techniques are disclosed for the cell/cluster formation of compute nodes and workload and processing resource scheduling. Compute nodes within an environment may be grouped (clustered) together to perform one or more designated workload tasks. The clustered compute nodes may be associated with (or assigned to) a workload cell formed to perform one or more identified task(s).

公开(公告)号：US11494212B2

公开(公告)日：2022-11-08

申请号：US16144388

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Ranganath Sunku ,  Dinesh Kumar ,  Irene Liew ,  Kavindya Deegala ,  Sravanthi Tangeda

IPC: G06F9/455 ,  G06F9/50 ,  H04L12/931 ,  G06F15/16 ,  H04L15/16 ,  H04L49/00 ,  H04L41/0823 ,  H04L12/70

Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.

公开(公告)号：US11888710B2

公开(公告)日：2024-01-30

申请号：US16140938

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Iosif Gasparakis ,  Malini Bhandaru ,  Ranganath Sunku

IPC: H04L41/5003 ,  G06F12/084 ,  G06F9/455 ,  H04L43/08 ,  H04L47/70 ,  G06F12/0864 ,  H04L67/568

CPC classification number: H04L41/5003 ,  G06F9/45558 ,  G06F12/084 ,  G06F12/0864 ,  H04L43/08 ,  H04L47/82 ,  H04L67/568 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45595 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/6032

Abstract: Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.

公开(公告)号：US20190042298A1

公开(公告)日：2019-02-07

申请号：US16144388

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Ranganath Sunku ,  Dinesh Kumar ,  Irene Liew ,  Kavindya Deegala ,  Sravanthi Tangeda

IPC: G06F9/455 ,  G06F9/50 ,  H04L12/931

Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.

公开(公告)号：US20190044828A1

公开(公告)日：2019-02-07

申请号：US16140938

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Iosif Gasparakis ,  Malini Bhandaru ,  Ranganath Sunku

IPC: H04L12/24 ,  G06F12/084 ,  G06F9/455 ,  H04L29/08 ,  H04L12/26 ,  H04L12/911

Abstract: Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.