公开(公告)号：US20180088652A1

公开(公告)日：2018-03-29

申请号：US15658337

申请日：2017-07-24

Applicant: Intel Corporation

Inventor： Seh W. Kwa ,  Neil W. Songer ,  Rob Gough ,  David J. Harriman

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/24

CPC classification number: G06F1/324 ,  G06F1/3209 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4265 ,  Y02B60/1235 ,  Y02D10/151

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

公开(公告)号：US10146290B2

公开(公告)日：2018-12-04

申请号：US15658337

申请日：2017-07-24

Applicant: Intel Corporation

Inventor： Seh W. Kwa ,  Neil W. Songer ,  Rob Gough ,  David J. Harriman

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/24

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

公开(公告)号：US09715269B2

公开(公告)日：2017-07-25

申请号：US14583333

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Seh W. Kwa ,  Neil Songer ,  Rob Gough ,  David J. Harriman

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/42 ,  G06F13/24

CPC classification number: G06F1/324 ,  G06F1/3209 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4265 ,  Y02B60/1235 ,  Y02D10/151

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

公开(公告)号：US20150127874A1

公开(公告)日：2015-05-07

申请号：US14583333

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Seh W. Kwa ,  Neil Songer ,  Rob Gough ,  David J. Harriman

IPC: G06F1/32 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F1/324 ,  G06F1/3209 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4265 ,  Y02B60/1235 ,  Y02D10/151

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract translation: 在一些实施例中，可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。 主机芯片组心跳的可用性可以被发送到外部设备，并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段，而且活动的断言是有利的，因为主机芯片组已经从 降低功耗状态。