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公开(公告)号：US10761579B2
公开(公告)日：2020-09-01
申请号：US15668771
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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公开(公告)号：US10146290B2
公开(公告)日：2018-12-04
申请号：US15658337
申请日：2017-07-24
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Neil W. Songer , Rob Gough , David J. Harriman
Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
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公开(公告)号：US20150257101A1
公开(公告)日：2015-09-10
申请号：US14595085
申请日：2015-01-12
Applicant: Intel Corporation
Inventor： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
CPC classification number: H04W52/0225 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3296 , G06F13/4282 , H04L43/0858 , Y02D10/151 , Y02D70/00 , Y02D70/142 , Y02D70/23
Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
Abstract translation: 对于一个公开的实施例，可以识别对于下游设备的至少一部分从第一状态到第二不同状态的转变。 第一和第二状态可以对应于与下游设备的至少一部分的活动有关的不同级别。 响应于所识别的一个或多个上游设备的转换，至少部分地基于服务等待时间来对应于服务等待时间的数据可被发送到上游设备以管理电力。 还公开了其他实施例。
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4.发明申请公开(公告)号：US20170371402A1
公开(公告)日：2017-12-28
申请号：US15191123
申请日：2016-06-23
Applicant: INTEL CORPORATION
Inventor： Barnes Cooper , Neil W. Songer
Abstract: Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.
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公开(公告)号：US09766673B2
公开(公告)日：2017-09-19
申请号：US14633438
申请日：2015-02-27
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
CPC classification number: G06F1/263 , G06F1/206 , G06F1/3212 , G06F1/324 , G06F15/00 , Y02D10/126 , Y02D10/16 , Y02D10/174
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20170177539A1
公开(公告)日：2017-06-22
申请号：US15453208
申请日：2017-03-08
Applicant: Intel Corporation
Inventor： Jaya L. Jeyaseelan , Jim Walsh , Robert E. Gough , Barnes Cooper , Neil W. Songer
CPC classification number: H04W52/0225 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3296 , G06F13/4282 , H04L43/0858 , Y02D10/151 , Y02D70/00 , Y02D70/142 , Y02D70/23
Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.
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公开(公告)号：US09459684B2
公开(公告)日：2016-10-04
申请号：US14101545
申请日：2013-12-10
Applicant: Intel Corporation
Inventor： Robert E. Gough , Seh W. Kwa , Neil W. Songer , Jaya L. Jeyaseelan , Barnes Cooper
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3215 , G06F1/3228
Abstract: For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
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公开(公告)号：US20160041595A1
公开(公告)日：2016-02-11
申请号：US14919780
申请日：2015-10-22
Applicant: Intel Corporation
Inventor： Barnes Cooper , Jeffrey R. Wilcox , Michael N. Derr , Neil W. Songer , Craig S. Forbell
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/3234 , G06F1/3243 , Y02D10/152
Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.
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公开(公告)号：US20180088652A1
公开(公告)日：2018-03-29
申请号：US15658337
申请日：2017-07-24
Applicant: Intel Corporation
Inventor： Seh W. Kwa , Neil W. Songer , Rob Gough , David J. Harriman
CPC classification number: G06F1/324 , G06F1/3209 , G06F13/24 , G06F13/4221 , G06F13/4265 , Y02B60/1235 , Y02D10/151
Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
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公开(公告)号：US09874922B2
公开(公告)日：2018-01-23
申请号：US14623764
申请日：2015-02-17
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , James G. Hermerding, II
CPC classification number: G06F1/3206 , G06F1/3203 , G06F1/3287 , G06F9/50 , Y02B70/126 , Y02D10/171
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.
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