公开(公告)号：US20180350712A1

公开(公告)日：2018-12-06

申请号：US15610327

申请日：2017-05-31

Applicant: INTEL CORPORATION

Inventor： Dinesh P. R. Thanu ,  Hemanth K. Dhavaleswarapu ,  John J. Beatty ,  Sachin Deshmukh

IPC: H01L23/36 ,  H01L23/498 ,  H01L21/48

Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.

公开(公告)号：US20210035886A1

公开(公告)日：2021-02-04

申请号：US16529639

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US11004768B2

公开(公告)日：2021-05-11

申请号：US16529639

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.