公开(公告)号：US10713052B2

公开(公告)日：2020-07-14

申请号：US16021974

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Karthik Sankaranarayanan ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Helia Naeimi

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

公开(公告)号：US20190004802A1

公开(公告)日：2019-01-03

申请号：US15637562

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Stephen J. Tarsa ,  Gokce Keskin ,  Gautham N. Chinya ,  Hong Wang

IPC: G06F9/38 ,  G06N3/04

Abstract: A processor, including: an execution unit including branching circuitry; a branch predictor, including a hard-to-predict (HTP) branch filter to identify an HTP branch; and a special branch predictor to receive identification of an HTP branch from the HTP branch filter, the special branch predictor including a convolutional neural network (CNN) branch predictor to predict a branching action for the HTP branch.

公开(公告)号：US20200183482A1

公开(公告)日：2020-06-11

申请号：US16370572

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Julien Sebot ,  Rangeen Basu Roy Chowdhury ,  Rustam Miftakhutdinov ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Eric Donkoh

IPC: G06F1/3234 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3228 ,  G06F9/50 ,  G06N5/04 ,  G06N20/00

Abstract: A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

公开(公告)号：US20180246762A1

公开(公告)日：2018-08-30

申请号：US15444390

申请日：2017-02-28

Applicant: Intel Corporation

Inventor： Stephen J. Tarsa ,  Gautham N. Chinya ,  Gokce Keskin ,  Hong Wang ,  Karthik Sankaranarayanan

IPC: G06F9/50

CPC classification number: G06F9/5083

Abstract: In one embodiment, a processor comprises a processor optimization unit. The processor optimization unit is to collect runtime information associated with a computing device, wherein the runtime information comprises information indicating a performance of the computing device during program execution. The processor optimization unit is further to receive runtime optimization information for the computing device, wherein the runtime optimization information comprises information associated with one or more runtime optimizations for the computing device, and wherein the runtime optimization information is determined based on an analysis of the collected runtime information. The processor optimization unit is further to perform the one or more runtime optimizations for the computing device based on the runtime optimization information.

公开(公告)号：US11048318B2

公开(公告)日：2021-06-29

申请号：US16370572

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Julien Sebot ,  Rangeen Basu Roy Chowdhury ,  Rustam Miftakhutdinov ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Eric Donkoh

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/324 ,  G06N20/00 ,  G06F9/50 ,  G06N5/04 ,  G06F1/3228

Abstract: A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

公开(公告)号：US10534613B2

公开(公告)日：2020-01-14

申请号：US15581791

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

IPC: G06F9/38 ,  G06N3/08

Abstract: Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.

公开(公告)号：US20180314524A1

公开(公告)日：2018-11-01

申请号：US15581791

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

IPC: G06F9/38 ,  G06N3/08

Abstract: Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.