Prefetcher for delinquent irregular loads

    公开(公告)号:US10713052B2

    公开(公告)日:2020-07-14

    申请号:US16021974

    申请日:2018-06-28

    申请人: Intel Corporation

    IPC分类号: G06F9/38 G06F9/30

    摘要: Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

    RUNTIME PROCESSOR OPTIMIZATION
    3.
    发明申请

    公开(公告)号:US20180246762A1

    公开(公告)日:2018-08-30

    申请号:US15444390

    申请日:2017-02-28

    申请人: Intel Corporation

    IPC分类号: G06F9/50

    CPC分类号: G06F9/5083

    摘要: In one embodiment, a processor comprises a processor optimization unit. The processor optimization unit is to collect runtime information associated with a computing device, wherein the runtime information comprises information indicating a performance of the computing device during program execution. The processor optimization unit is further to receive runtime optimization information for the computing device, wherein the runtime optimization information comprises information associated with one or more runtime optimizations for the computing device, and wherein the runtime optimization information is determined based on an analysis of the collected runtime information. The processor optimization unit is further to perform the one or more runtime optimizations for the computing device based on the runtime optimization information.