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公开(公告)号：US11966281B2
公开(公告)日：2024-04-23
申请号：US17723383
申请日：2022-04-18
Applicant: Intel Corporation
Inventor： Sundar Nadathur , Pratik M. Marolia , Henry M. Mitchel , Joseph J. Grecco , Utkarsh Y. Kakaiya , David A. Munday
CPC classification number: G06F11/0793 , G06F11/0706 , G06F11/0721 , G06F11/0751
Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
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公开(公告)号：US20220245022A1
公开(公告)日：2022-08-04
申请号：US17723383
申请日：2022-04-18
Applicant: Intel Corporation
Inventor： Sundar Nadathur , Pratik M. Marolia , Henry M. Mitchel , Joseph J. Grecco , Utkarsh Y. Kakaiya , David A. Munday
Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
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3.发明申请公开(公告)号：US20220158850A1
公开(公告)日：2022-05-19
申请号：US17665078
申请日：2022-02-04
Applicant: Intel Corporation
Inventor： Ned Smith , Rajesh Poornachandran , Sundar Nadathur , Abdul M. Bailey
Abstract: A system includes a host processor operable to communicate with a remote requestor to perform operations for attesting a trusted system. The system also includes a hardware acceleration coprocessor coupled to the host processor. The host processor is further operable to offload at least some of the operations onto the hardware acceleration coprocessor to free up processing power on the host processor.
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公开(公告)号：US20240126615A1
公开(公告)日：2024-04-18
申请号：US18538364
申请日：2023-12-13
Applicant: Intel Corporation
Inventor： Sundar Nadathur , Akhilesh Thyagaturu , Jonathan L. Kyle , Scott M. Baker , Woojoong Kim
CPC classification number: G06F9/505 , G06F9/5044 , G06F9/5072 , G06F9/5088 , G06F11/3433 , G06F11/3442 , G06F2209/501 , G06F2209/5019 , G06F2209/508
Abstract: Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.
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公开(公告)号：US11307925B2
公开(公告)日：2022-04-19
申请号：US15940779
申请日：2018-03-29
Applicant: Intel Corporation
Inventor： Sundar Nadathur , Pratik M. Marolia , Henry M. Mitchel , Joseph J. Grecco , Utkarsh Y. Kakaiya , David A. Munday
Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190123912A1
公开(公告)日：2019-04-25
申请号：US16231172
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Ned Smith , Rajesh Poornachandran , Sundar Nadathur , Abdul M. Bailey
Abstract: A system for supporting Enhanced Privacy Identification (EPID) is provided. The system may include a host processor operable to communicate with a remote requestor, where the host processor needs to perform signature revocation checking in accordance with EPID. To perform signature revocation checking, the host processor has to perform either a sign or verify operation. The host processor may offload the sign/verify operation onto one or more associated hardware acceleration coprocessors. A programmable coprocessor may be dynamically configured to perform the desired number of sign/verify functions in accordance with the requirements of the current workload.
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7.发明公开公开(公告)号：US20240248792A1
公开(公告)日：2024-07-25
申请号：US18622897
申请日：2024-03-30
Applicant: Intel Corporation
Inventor： Sundar Nadathur , Pratik M. Marolia , Henry M. Mitchel , Joseph J. Grecco , Utkarsh Y. Kakaiya , David A. Munday
IPC: G06F11/07
CPC classification number: G06F11/0793 , G06F11/0706 , G06F11/0721 , G06F11/0751
Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
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8.发明授权公开(公告)号：US11265172B2
公开(公告)日：2022-03-01
申请号：US16231172
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Ned Smith , Rajesh Poornachandran , Sundar Nadathur , Abdul M. Bailey
Abstract: A system for supporting Enhanced Privacy Identification (EPID) is provided. The system may include a host processor operable to communicate with a remote requestor, where the host processor needs to perform signature revocation checking in accordance with EPID. To perform signature revocation checking, the host processor has to perform either a sign or verify operation. The host processor may offload the sign/verify operation onto one or more associated hardware acceleration coprocessors. A programmable coprocessor may be dynamically configured to perform the desired number of sign/verify functions in accordance with the requirements of the current workload.
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9.发明申请公开(公告)号：US20190042350A1
公开(公告)日：2019-02-07
申请号：US15940779
申请日：2018-03-29
Applicant: Intel Corporation
Inventor： Sundar Nadathur , Pratik M. Marolia , Henry M. Mitchel , Joseph J. Grecco , Utkarsh Y. Kakaiya , David A. Munday
Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
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公开(公告)号：US12112204B2
公开(公告)日：2024-10-08
申请号：US17884244
申请日：2022-08-09
Applicant: Intel Corporation
Inventor： Pratik M. Marolia , Aaron J. Grier , Henry M. Mitchel , Joseph Grecco , Michael C. Adler , Utkarsh Y. Kakaiya , Joshua D. Fender , Sundar Nadathur , Nagabhushan Chitlur
CPC classification number: G06F9/5027 , G06F9/468 , G06F9/4843 , G06F9/5044
Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.
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