中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.013 seconds)

    Coherency Domain Cacheline State Tracking
    1.
    发明公开
    Coherency Domain Cacheline State Tracking 审中-公开

    公开(公告)号：US20240037038A1

    公开(公告)日：2024-02-01

    申请号：US18478621

    申请日：2023-09-29

    Applicant: Intel Corporation

    Inventor： Nagabhushan Chitlur ,  Darren Michael Andrus ,  Kelly Hagen ,  Randall Bright

    IPC: G06F12/0831 ,  G06F12/0817 ,  G06F13/42

    CPC classification number: G06F12/0835 ,  G06F12/0817 ,  G06F13/4234

    Abstract: Circuitry, systems, and methods are provided for an integrated circuit including an acceleration function unit to provide hardware acceleration for a host device. The integrated circuit may also include interface circuitry including a cache coherency bridge/agent including a device cache to resolve coherency with a host cache of the host device. The interface circuitry may also include cacheline state tracker circuitry to track states of cachelines of the device cache and the host cache. The cacheline state tracker circuitry provides insights to expected state changes based on states of the cachelines of the device cache, the host cache, and a type of operation performed.

    Hetergeneous processor apparatus and method
    2.
    发明授权
    Hetergeneous processor apparatus and method 有权
    杀菌处理器装置及方法

    公开(公告)号：US09329900B2

    公开(公告)日：2016-05-03

    申请号：US13730539

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

    IPC: G06F9/50 ,  G06F9/455 ,  G06F15/80

    CPC classification number: G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

    Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

    Execution unit accelerator
    5.
    发明授权
    Execution unit accelerator 有权

    公开(公告)号：US10929134B2

    公开(公告)日：2021-02-23

    申请号：US16457238

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Radhakrishna Sripada ,  Peter Yiannacouras ,  Josh Triplett ,  Nagabhushan Chitlur ,  Kalyan Kondapally

    IPC: G06T1/20 ,  G06F9/30

    Abstract: A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.

    CIRCUIT CARD WITH COHERENT INTERCONNECT
    6.
    发明申请
    CIRCUIT CARD WITH COHERENT INTERCONNECT 审中-公开

    公开(公告)号：US20190044293A1

    公开(公告)日：2019-02-07

    申请号：US15952741

    申请日：2018-04-13

    Applicant: Intel Corporation

    Inventor： Dirk Blevins ,  Gene F. Young ,  Sudeep Puligundla ,  Todd Langley ,  Kevin Bross ,  Nagabhushan Chitlur

    IPC: H01R27/02 ,  H01R12/70 ,  H05K1/11 ,  H05K7/14

    Abstract: Apparatuses and systems associated with expansion card design with a coherent connector to provide for coherent communication are disclosed herein. In embodiments, a circuit card may comprise an integrated circuit (IC), a first connector to couple the IC to a processor of a computer device, the first connector to provide for non-coherent communication between the IC and the processor, and a second connector to couple the IC to the processor, the second connector to provide for coherent communication between the IC and the processor. Other embodiments may be described and/or claimed.

Patent Agency Ranking