公开(公告)号：US20190004955A1

公开(公告)日：2019-01-03

申请号：US15640534

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Michael C. Adler ,  Chiachen Chou ,  Neal C. Crago ,  Kermin Fleming ,  Kent D. Glossop ,  Aamer Jaleel ,  Pratik M. Marolia ,  Simon C. Steely, JR. ,  Samantika S. Sury

IPC: G06F12/0862 ,  G06F12/0802 ,  H03K19/177 ,  G06F15/78

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F15/7867 ,  G06F15/8015 ,  G06F17/505 ,  G06F2212/6026 ,  G11C8/12 ,  H03K19/17736 ,  H03K19/17756 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

公开(公告)号：US20190042518A1

公开(公告)日：2019-02-07

申请号：US15836856

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Stephen S. Chang ,  Nagabhushan Chitlur ,  Michael C. Adler

IPC: G06F13/42 ,  G06N3/08 ,  G06F9/455

Abstract: There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.

公开(公告)号：US10387319B2

公开(公告)日：2019-08-20

申请号：US15640534

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Michael C. Adler ,  Chiachen Chou ,  Neal C. Crago ,  Kermin Fleming ,  Kent D. Glossop ,  Aamer Jaleel ,  Pratik M. Marolia ,  Simon C. Steely, Jr. ,  Samantika S. Sury

IPC: G06F12/0802 ,  G06F15/00 ,  G06F12/0862 ,  H03K19/177 ,  G06F15/78 ,  G11C8/12 ,  G06F17/50 ,  G06F15/80

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.

公开(公告)号：US10331583B2

公开(公告)日：2019-06-25

申请号：US14037468

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Bushra Ahsan ,  Michael C. Adler ,  Neal C. Crago ,  Joel S. Emer ,  Aamer Jaleel ,  Angshuman Parashar ,  Michael I. Pellauer

IPC: G06F13/00 ,  G06F13/16 ,  G06F12/06

Abstract: A processing device for executing distributed memory operations using spatial processing units (SPU) connected by distributed channels is disclosed. A distributed channel may or may not be associated with memory operations, such as load operations or store operations. Distributed channel information is obtained for an algorithm to be executed by a group of spatially distributed processing elements. The group of spatially distributed processing elements can be connected to a shared memory controller. For each distributed channel in the distributed channel information, one or more of the group of spatially distributed processing elements may be associated with the distributed channel based on the algorithm. By associating the spatially distributed processing elements to a distributed channel, the functionality of the processing element can vary depending on the algorithm mapped onto the SPU.

公开(公告)号：US11194753B2

公开(公告)日：2021-12-07

申请号：US15836856

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Stephen S. Chang ,  Nagabhushan Chitlur ,  Michael C. Adler

IPC: G06F3/00 ,  G06F13/42 ,  G06N3/08 ,  G06F9/455

Abstract: There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.

公开(公告)号：US20190303312A1

公开(公告)日：2019-10-03

申请号：US16443717

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Bushra Ahsan ,  Michael C. Adler ,  Neal C. Crago ,  Joel S. Emer ,  Aamer Jaleel ,  Angshuman Parashar ,  Michael I. Pellauer

IPC: G06F13/16

Abstract: A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

公开(公告)号：US12112204B2

公开(公告)日：2024-10-08

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Aaron J. Grier ,  Henry M. Mitchel ,  Joseph Grecco ,  Michael C. Adler ,  Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/468 ,  G06F9/4843 ,  G06F9/5044

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US11416300B2

公开(公告)日：2022-08-16

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. Marolia ,  Aaron J. Grier ,  Henry M. Mitchel ,  Joseph Grecco ,  Michael C. Adler ,  Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US10853276B2

公开(公告)日：2020-12-01

申请号：US16443717

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Bushra Ahsan ,  Michael C. Adler ,  Neal C. Crago ,  Joel S. Emer ,  Aamer Jaleel ,  Angshuman Parashar ,  Michael I. Pellauer

IPC: G06F13/16 ,  G06F12/06

Abstract: A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

公开(公告)号：US20190004878A1

公开(公告)日：2019-01-03

申请号：US15640542

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Michael C. Adler ,  Kermin Fleming ,  Kent D. Glossop ,  Simon C. Steely, JR.

IPC: G06F9/54 ,  G06F9/30 ,  G06F21/62 ,  G06F13/16

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of two dataflow graphs each comprising a plurality of nodes, wherein a first dataflow graph and a second dataflow graph are be overlaid into a first and second portion, respectively, of the interconnect network and a first and second subset, respectively, of the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the first and second subsets of the plurality of processing elements are to perform a first and second operation, respectively, when incoming first and second, respectively, operand sets arrive at the plurality of processing elements.