公开(公告)号：US20180331900A1

公开(公告)日：2018-11-15

申请号：US15592799

申请日：2017-05-11

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Joseph Grecco ,  Prashant Sethi ,  Nagabhushan Chitlur ,  Pratik M. Marolia ,  Henry M. Mitchel

IPC: H04L12/24 ,  G06F9/455

CPC classification number: H04L41/0813 ,  G06F9/455 ,  H04L12/40

Abstract: An embodiment of a device manager apparatus may include a request processor to process a request for a reconfiguration of a reconfigurable device, a configuration controller communicatively coupled to the request processor to reconfigure the reconfigurable device based on the request, and a pseudo-device manager communicatively coupled to the request processor to create a pseudo device based on the request which corresponds to a functionality of the reconfiguration.

公开(公告)号：US20190109593A1

公开(公告)日：2019-04-11

申请号：US15942919

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Joshua D. Fender

IPC: H03K19/177

CPC classification number: H03K19/17768 ,  H03K19/17728 ,  H03K19/17764

Abstract: A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.

公开(公告)号：US12112204B2

公开(公告)日：2024-10-08

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Aaron J. Grier ,  Henry M. Mitchel ,  Joseph Grecco ,  Michael C. Adler ,  Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/468 ,  G06F9/4843 ,  G06F9/5044

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US11416300B2

公开(公告)日：2022-08-16

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. Marolia ,  Aaron J. Grier ,  Henry M. Mitchel ,  Joseph Grecco ,  Michael C. Adler ,  Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US10541687B2

公开(公告)日：2020-01-21

申请号：US15942919

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Joshua D. Fender

IPC: G06F7/38 ,  H03K19/173

Abstract: A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.

公开(公告)号：US09935638B1

公开(公告)日：2018-04-03

申请号：US15628888

申请日：2017-06-21

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Joshua D. Fender

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17768 ,  H03K19/17728 ,  H03K19/17764

Abstract: A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.