公开(公告)号：US12009813B1

公开(公告)日：2024-06-11

申请号：US17827570

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park ,  Bishnu Prasad Patra

IPC: H03K17/92 ,  G06N10/40 ,  H03M1/66 ,  H10N60/10

CPC classification number: H03K17/92 ,  G06N10/40 ,  H03M1/66 ,  H10N60/11 ,  H10N60/128

Abstract: Technologies for the reduction of memory effects in a capacitor are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes an array of capacitors that can be charged to a voltage based on a voltage to be applied to a gate of the quantum processor. The capacitors in the array of capacitors are connected to the gate one at a time, charging up a parasitic capacitance. As more capacitors are switched, the voltage on the gate approaches a target voltage with an exponentially-decreasing voltage error.

公开(公告)号：US11955965B1

公开(公告)日：2024-04-09

申请号：US17827590

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park ,  Bishnu Prasad Patra

IPC: H03K17/693 ,  G06N10/40 ,  H03K17/687

CPC classification number: H03K17/693 ,  G06N10/40 ,  H03K17/6874

Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.

公开(公告)号：US20240104413A1

公开(公告)日：2024-03-28

申请号：US17954131

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Todor Mladenov ,  Sahar Daraeizadeh ,  Anne Matsuura

IPC: G06N10/20

CPC classification number: G06N10/20

Abstract: Technologies for a hybrid digital/analog processor for a quantum computer are disclosed. In the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. The digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. The analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. The integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.

公开(公告)号：US20230153125A1

公开(公告)日：2023-05-18

申请号：US17527875

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park

IPC: G06F9/448 ,  G06N10/00

CPC classification number: G06F9/4498 ,  G06N10/00

Abstract: Technologies for signal conditioning for signals for qubits are disclosed. In the illustrative embodiment, a finite impulse response filter is applied to a control signal for a target qubit to filter out a frequency corresponding to a collateral qubit. An infinite impulse response filter is then applied to the signal after the finite impulse response filter, which amplifies some of the frequencies filtered out by the finite impulse response, narrowing the bandwidth that is filtered out. Such an approach reduces the attenuation of the signal and can be used to reduce memory requirements of quantum/classical interface circuitry.

公开(公告)号：US20250021849A1

公开(公告)日：2025-01-16

申请号：US18220212

申请日：2023-07-10

Applicant: Intel Corporation

Inventor： Sahar Daraeizadeh ,  Todor Mladenov ,  Xiang Zou ,  Anne Matsuura

IPC: G06N10/20

Abstract: Apparatus and method for a quantum control processor. For example, one embodiment of a QCP comprises: instruction fetch logic to fetch instructions from a memory, the instructions including quantum instructions; decode logic to decode the quantum instructions into a first plurality of quantum microoperations; translation logic translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; and issue logic to synchronously issue the second plurality of quantum microoperations in parallel to the plurality of quantum controller cores.

公开(公告)号：US20230186142A1

公开(公告)日：2023-06-15

申请号：US17549154

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Todor Mladenov ,  JongSeok Park ,  Stefano Pellerano ,  Sushil Subramanian

IPC: G06N10/80 ,  G06N10/60

CPC classification number: G06N10/80 ,  G06N10/60 ,  G06N10/40

Abstract: Technologies for high-speed interfaces for cryogenic quantum control are disclosed. In the illustrative embodiment, a die for quantum/classical interface circuitry includes digital circuitry operating in a first clock domain and analog circuitry operating in a second clock domain. Clock domain crossing circuitry facilitates asynchronous data transfer from the digital circuitry to the analog circuitry. The illustrative clock domain crossing circuitry includes a first asynchronous first-in-first-out (FIFO) queue at the border of the first clock domain. The first asynchronous FIFO queue is connected to a second asynchronous FIFO queue at the border of the second clock domain.