公开(公告)号：US12248848B2

公开(公告)日：2025-03-11

申请号：US17340173

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Ravi Pillarisetty ,  Jong Seok Park ,  Todor M. Mladenov

IPC: G06N10/00 ,  H03M1/66

Abstract: Quantum circuit assemblies that employ active pulse shaping in order to be able to control states of a plurality of qubits with signal pulses propagated over a shared signal propagation channel are disclosed. An example quantum circuit assembly includes a quantum circuit component that includes a first qubit, associated with a first frequency to control the state of the first qubit, and a second qubit, associated with a second frequency to control the state of the second qubit. A shared transmission channel is coupled to the first and second qubits. The assembly further includes a signal pulse generation circuit, configured to generate a signal pulse to be propagated over the shared transmission channel to control the state of the first qubit, where the signal pulse has a center frequency at the first frequency, a bandwidth that includes the second frequency, and a notch at the second frequency.

公开(公告)号：US20230153125A1

公开(公告)日：2023-05-18

申请号：US17527875

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park

IPC: G06F9/448 ,  G06N10/00

CPC classification number: G06F9/4498 ,  G06N10/00

Abstract: Technologies for signal conditioning for signals for qubits are disclosed. In the illustrative embodiment, a finite impulse response filter is applied to a control signal for a target qubit to filter out a frequency corresponding to a collateral qubit. An infinite impulse response filter is then applied to the signal after the finite impulse response filter, which amplifies some of the frequencies filtered out by the finite impulse response, narrowing the bandwidth that is filtered out. Such an approach reduces the attenuation of the signal and can be used to reduce memory requirements of quantum/classical interface circuitry.

公开(公告)号：US20220113977A1

公开(公告)日：2022-04-14

申请号：US17070798

申请日：2020-10-14

Applicant: Intel Corporation

Inventor： Ilya Klochkov ,  Sushil Subramanian ,  Dileep Kurian ,  Saksham Soni ,  Venkataramana Parvatha

IPC: G06F9/38 ,  G06N10/00

Abstract: Apparatus and method for correcting quantum bit states. For example, one embodiment of an apparatus comprises: a phase error evaluator to evaluate a quantum instruction sequence of a quantum program to determine accumulated phase error; phase correction hardware logic to insert one or more phase correction instructions into the quantum instruction sequence to generate a modified quantum instruction sequence to correct the accumulated phase error; and wherein the modified quantum instruction sequence or a translated version thereof is to be executed by a qubit controller chip.

公开(公告)号：US20230186142A1

公开(公告)日：2023-06-15

申请号：US17549154

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Todor Mladenov ,  JongSeok Park ,  Stefano Pellerano ,  Sushil Subramanian

IPC: G06N10/80 ,  G06N10/60

CPC classification number: G06N10/80 ,  G06N10/60 ,  G06N10/40

Abstract: Technologies for high-speed interfaces for cryogenic quantum control are disclosed. In the illustrative embodiment, a die for quantum/classical interface circuitry includes digital circuitry operating in a first clock domain and analog circuitry operating in a second clock domain. Clock domain crossing circuitry facilitates asynchronous data transfer from the digital circuitry to the analog circuitry. The illustrative clock domain crossing circuitry includes a first asynchronous first-in-first-out (FIFO) queue at the border of the first clock domain. The first asynchronous FIFO queue is connected to a second asynchronous FIFO queue at the border of the second clock domain.

公开(公告)号：US20230155573A1

公开(公告)日：2023-05-18

申请号：US17528453

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Stefano Pellerano ,  JongSeok Park ,  Lester F. Lampert ,  Sushil Subramanian ,  Thomas F. Watson

IPC: H03H11/28

CPC classification number: H03H11/28

Abstract: Technologies for impedance matching networks for qubits are disclosed. In one illustrative embodiment, an impedance matching network matches a 50 Ohm transmission line to a spin qubit with a state-dependent resistance of 100 kiloohms to 105 kiloohms. The illustrative impedance matching network is tunable, allowing the impedance transformation ratio to be changed without significantly changing the matching frequency of the impedance matching network. In some embodiments, the impedance matching network matches a 50 Ohm transmission line to a lower-resistance state of a qubit. In other embodiments, the impedance matching network matches a 50 Ohm transmission line to an impedance value in between a lower-resistance state and a higher-resistance state of a qubit.

公开(公告)号：US12050966B2

公开(公告)日：2024-07-30

申请号：US17555717

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Florian Luethi ,  Hubert C. George ,  Felix Frederic Leonhard Borjans ,  Simon Schaal ,  Lester Lampert ,  Thomas Francis Watson ,  Jeanette M. Roberts ,  Jong Seok Park ,  Sushil Subramanian ,  Stefano Pellerano

IPC: G06N10/00 ,  H01L29/12

CPC classification number: G06N10/00 ,  H01L29/12

Abstract: An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

公开(公告)号：US12009813B1

公开(公告)日：2024-06-11

申请号：US17827570

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park ,  Bishnu Prasad Patra

IPC: H03K17/92 ,  G06N10/40 ,  H03M1/66 ,  H10N60/10

CPC classification number: H03K17/92 ,  G06N10/40 ,  H03M1/66 ,  H10N60/11 ,  H10N60/128

Abstract: Technologies for the reduction of memory effects in a capacitor are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes an array of capacitors that can be charged to a voltage based on a voltage to be applied to a gate of the quantum processor. The capacitors in the array of capacitors are connected to the gate one at a time, charging up a parasitic capacitance. As more capacitors are switched, the voltage on the gate approaches a target voltage with an exponentially-decreasing voltage error.

公开(公告)号：US20230196152A1

公开(公告)日：2023-06-22

申请号：US17555717

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Florian Luethi ,  Hubert C. George ,  Felix Frederic Leonhard Borjans ,  Simon Schaal ,  Lester Lampert ,  Thomas Francis Watson ,  Jeanette M. Roberts ,  Jong Seok Park ,  Sushil Subramanian ,  Stefano Pellerano

IPC: G06N10/00 ,  H01L29/12

CPC classification number: G06N10/00 ,  H01L29/12

Abstract: An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

公开(公告)号：US20240330726A1

公开(公告)日：2024-10-03

申请号：US18740726

申请日：2024-06-12

Applicant: Intel Corporation

Inventor： Florian Luethi ,  Hubert C. George ,  Felix Frederic Leonhard Borjans ,  Simon Schaal ,  Lester Lampert ,  Thomas Francis Watson ,  Jeanette M. Roberts ,  Jong Seok Park ,  Sushil Subramanian ,  Stefano Pellerano

IPC: G06N10/00 ,  H01L29/12

CPC classification number: G06N10/00 ,  H01L29/12

Abstract: An array of quantum dot qubits (e.g., an array of spin qubits) relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the electric dipole spin resonance (EDSR) of the qubits. Quantum dot devices disclosed herein use microcoil arrangements for providing a gradient magnetic field, the microcoil arrangements integrated on the same chip (e.g., on the same die or wafer) as quantum dot qubits themselves. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

公开(公告)号：US11955965B1

公开(公告)日：2024-04-09

申请号：US17827590

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Sushil Subramanian ,  Stefano Pellerano ,  Todor Mladenov ,  JongSeok Park ,  Bishnu Prasad Patra

IPC: H03K17/693 ,  G06N10/40 ,  H03K17/687

CPC classification number: H03K17/693 ,  G06N10/40 ,  H03K17/6874

Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.