公开(公告)号：US20160245841A1

公开(公告)日：2016-08-25

申请号：US15051856

申请日：2016-02-24

Applicant: Intel Corporation

Inventor： Qing MA ,  Valluri RAO ,  Feras EID ,  Kevin LIN ,  Weng Hong TEH ,  Johanna SWAN ,  Robert SANKMAN

IPC: G01P15/097

CPC classification number: G01P15/097 ,  G01P15/105 ,  G01P15/18

Abstract: An accelerometer includes a mass, suspended by a beam, and associated conductive paths. Each conductive path is subjected to a magnetic field, such that, when a time varying signal is applied to the conductive paths, a characteristic resonant frequency is produced, and when the mass experiences an acceleration, a respective change in the resonant frequency is produced that may be interpreted as acceleration data. Embodiments include methods of manufacturing an accelerometer and systems and devices incorporating the accelerometer.

Abstract translation: 加速度计包括由梁悬挂的质量块和相关联的导电路径。 每个导电路径受到磁场的影响，使得当对导电路径施加时变信号时，产生特性谐振频率，并且当质量经历加速度时，产生谐振频率的相应变化， 可以解释为加速度数据。 实施例包括制造加速度计的方法和结合有加速度计的系统和装置。

公开(公告)号：US20160291641A1

公开(公告)日：2016-10-06

申请号：US15037639

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Brian S. DOYLE ,  Han Wui THEN ,  Valluri RAO ,  Niloy MUKHERJEE ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: G06F1/16 ,  H04M1/02 ,  H05K3/30 ,  H05K1/02 ,  H05K3/46

CPC classification number: G06F1/1652 ,  G06F1/1626 ,  G06F1/1643 ,  G06F1/1656 ,  G06F2203/04102 ,  G06F2203/04103 ,  G09F9/00 ,  G09G3/2092 ,  G09G2300/0426 ,  G09G2380/02 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1266 ,  H04M1/0268 ,  H05K1/028 ,  H05K1/0296 ,  H05K3/30 ,  H05K3/4682

Abstract: A flexible electronic computing device is described. In one embodiment, a flexible display is formed on a flexible substrate. A plurality of electronic components are attached to the flexible substrate. A plurality of conductive signal lines are formed on the flexible substrate, the signal lines electrically coupling the electronic components to the flexible display.

Abstract translation: 描述了一种灵活的电子计算设备。 在一个实施例中，柔性显示器形成在柔性基板上。 多个电子部件附接到柔性基板。 多个导电信号线形成在柔性基板上，信号线将电子部件电耦合到柔性显示器。

公开(公告)号：US20190244936A1

公开(公告)日：2019-08-08

申请号：US16386200

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Valluri RAO ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack KAVALIEROS

IPC: H01L25/07 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8258 ,  H01L29/778 ,  H01L25/00 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.