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    SELECTIVE METAL REMOVAL FOR CONDUCTIVE INTERCONNECTS IN INTEGRATED CIRCUITRY
    1.
    发明申请
    SELECTIVE METAL REMOVAL FOR CONDUCTIVE INTERCONNECTS IN INTEGRATED CIRCUITRY 审中-公开

    公开(公告)号：US20200185226A1

    公开(公告)日：2020-06-11

    申请号：US16334324

    申请日：2016-09-30

    申请人： Intel Corporation

    发明人： Kevin LIN ,  Rahim KASIM ,  Manish CHANDHOK ,  Florian Gstrein

    IPC分类号： H01L21/302 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

    摘要： Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

    RESONATOR STRUCTURE ENCAPSULATION
    2.
    发明申请
    RESONATOR STRUCTURE ENCAPSULATION 审中-公开

    公开(公告)号：US20190267961A1

    公开(公告)日：2019-08-29

    申请号：US16348830

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： Kevin LIN ,  Kimin JUN ,  Edris MOHAMMED

    IPC分类号： H03H3/02 ,  H03H9/17

    摘要： The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.

    ACCELEROMETER AND METHOD OF MAKING SAME
    4.
    发明申请
    ACCELEROMETER AND METHOD OF MAKING SAME 审中-公开
    加速度计及其制作方法

    公开(公告)号：US20160245841A1

    公开(公告)日：2016-08-25

    申请号：US15051856

    申请日：2016-02-24

    申请人： Intel Corporation

    发明人： Qing MA ,  Valluri RAO ,  Feras EID ,  Kevin LIN ,  Weng Hong TEH ,  Johanna SWAN ,  Robert SANKMAN

    IPC分类号： G01P15/097

    CPC分类号： G01P15/097 ,  G01P15/105 ,  G01P15/18

    摘要： An accelerometer includes a mass, suspended by a beam, and associated conductive paths. Each conductive path is subjected to a magnetic field, such that, when a time varying signal is applied to the conductive paths, a characteristic resonant frequency is produced, and when the mass experiences an acceleration, a respective change in the resonant frequency is produced that may be interpreted as acceleration data. Embodiments include methods of manufacturing an accelerometer and systems and devices incorporating the accelerometer.

    摘要翻译： 加速度计包括由梁悬挂的质量块和相关联的导电路径。 每个导电路径受到磁场的影响，使得当对导电路径施加时变信号时，产生特性谐振频率，并且当质量经历加速度时，产生谐振频率的相应变化， 可以解释为加速度数据。 实施例包括制造加速度计的方法和结合有加速度计的系统和装置。

    CORE FILL TO REDUCE DISHING AND METAL PILLAR FILL TO INCREASE METAL DENSITY OF INTERCONNECTS
    7.
    发明申请
    CORE FILL TO REDUCE DISHING AND METAL PILLAR FILL TO INCREASE METAL DENSITY OF INTERCONNECTS 审中-公开

    公开(公告)号：US20190393147A1

    公开(公告)日：2019-12-26

    申请号：US16017962

    申请日：2018-06-25

    申请人： Intel Corporation

    发明人： Kevin LIN

    IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    摘要： An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.

    CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING
    9.
    发明申请
    CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING 审中-公开

    公开(公告)号：US20200303238A1

    公开(公告)日：2020-09-24

    申请号：US16358520

    申请日：2019-03-19

    申请人： Intel Corporation

    发明人： Ehren MANNEBACH ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Hui Jae YOO ,  Patrick MORROW ,  Kevin LIN

    IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L21/762 ,  H01L21/683 ,  H01L23/31

    摘要： Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.