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    PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES
    1.
    发明申请
    PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES 有权

    公开(公告)号：US20220068861A1

    公开(公告)日：2022-03-03

    申请号：US17523787

    申请日：2021-11-10

    申请人： Intel Corporation

    发明人： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

    IPC分类号： H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538

    摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

    ACCELEROMETER AND METHOD OF MAKING SAME
    5.
    发明申请
    ACCELEROMETER AND METHOD OF MAKING SAME 审中-公开
    加速度计及其制作方法

    公开(公告)号：US20160245841A1

    公开(公告)日：2016-08-25

    申请号：US15051856

    申请日：2016-02-24

    申请人： Intel Corporation

    发明人： Qing MA ,  Valluri RAO ,  Feras EID ,  Kevin LIN ,  Weng Hong TEH ,  Johanna SWAN ,  Robert SANKMAN

    IPC分类号： G01P15/097

    CPC分类号： G01P15/097 ,  G01P15/105 ,  G01P15/18

    摘要： An accelerometer includes a mass, suspended by a beam, and associated conductive paths. Each conductive path is subjected to a magnetic field, such that, when a time varying signal is applied to the conductive paths, a characteristic resonant frequency is produced, and when the mass experiences an acceleration, a respective change in the resonant frequency is produced that may be interpreted as acceleration data. Embodiments include methods of manufacturing an accelerometer and systems and devices incorporating the accelerometer.

    摘要翻译： 加速度计包括由梁悬挂的质量块和相关联的导电路径。 每个导电路径受到磁场的影响，使得当对导电路径施加时变信号时，产生特性谐振频率，并且当质量经历加速度时，产生谐振频率的相应变化， 可以解释为加速度数据。 实施例包括制造加速度计的方法和结合有加速度计的系统和装置。

    HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
    9.
    发明申请
    HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE 有权

    公开(公告)号：US20220130789A1

    公开(公告)日：2022-04-28

    申请号：US17570255

    申请日：2022-01-06

    申请人： Intel Corporation

    发明人： Weng Hong TEH ,  Chia-Pin CHIU

    IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18

    摘要： Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

    HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
    10.
    发明申请
    HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE 有权

    公开(公告)号：US20210043596A1

    公开(公告)日：2021-02-11

    申请号：US17077996

    申请日：2020-10-22

    申请人： Intel Corporation

    发明人： Weng Hong TEH ,  Chia-Pin CHIU

    IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18

    摘要： Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.