-
公开(公告)号:US20240241446A1
公开(公告)日:2024-07-18
申请号:US18620262
申请日:2024-03-28
Applicant: Intel Corporation
Inventor: Marvin Paik , Charles H. Wallace , Leonard Guler , Elliot N. Tan , Shengsi Liu , Vivek Vishwakarma , Izabela Samek , Mohammadreza Soleymaniha
IPC: G03F7/20 , G03F7/00 , H01L21/027
CPC classification number: G03F7/2022 , G03F7/2004 , G03F7/201 , G03F7/70033 , G03F7/7005 , G03F7/70525 , G03F7/7055 , G03F7/70725 , H01L21/0275
Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.
-
2.
公开(公告)号:US20240355915A1
公开(公告)日:2024-10-24
申请号:US18137731
申请日:2023-04-21
Applicant: Intel Corporation
Inventor: Leonard P. Guler , Clifford J. Engel , Debaleena Nandi , Gary Allen , Nicholas A. Thomson , Saurabh Acharya , Umang Desai , Vivek Vishwakarma , Charles H. Wallace
IPC: H01L29/775 , H01L27/088 , H01L29/06 , H01L29/423
CPC classification number: H01L29/775 , H01L27/088 , H01L29/0673 , H01L29/42392
Abstract: Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.
-