公开(公告)号：US20210202472A1

公开(公告)日：2021-07-01

申请号：US16728111

申请日：2019-12-27

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US20230089395A1

公开(公告)日：2023-03-23

申请号：US17448373

申请日：2021-09-22

申请人： INTEL CORPORATION

发明人： Benjamin Orr ,  Nicholas A. Thomson ,  Ayan Kar ,  Nathan D. Jack ,  Kalyan C. Kolluru ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

IPC分类号： H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

摘要： Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

公开(公告)号：US20210167180A1

公开(公告)日：2021-06-03

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/423 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

公开(公告)号：US20240355915A1

公开(公告)日：2024-10-24

申请号：US18137731

申请日：2023-04-21

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Clifford J. Engel ,  Debaleena Nandi ,  Gary Allen ,  Nicholas A. Thomson ,  Saurabh Acharya ,  Umang Desai ,  Vivek Vishwakarma ,  Charles H. Wallace

IPC分类号： H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

摘要： Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.

公开(公告)号：US20240088136A1

公开(公告)日：2024-03-14

申请号：US17943557

申请日：2022-09-13

申请人： Intel Corporation

发明人： Ayan Kar ,  Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Benjamin Orr

IPC分类号： H01L27/02

CPC分类号： H01L27/027

摘要： An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.

公开(公告)号：US20230420578A1

公开(公告)日：2023-12-28

申请号：US17848660

申请日：2022-06-24

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Vijaya Bhaskara Neeli ,  Said Rami ,  Saurabh Morarka ,  Karthik Krishaswamy ,  Mauro J. Kobrinsky

IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/93 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/42392

摘要： A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.

公开(公告)号：US20230402449A1

公开(公告)日：2023-12-14

申请号：US18457453

申请日：2023-08-29

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0288 ,  H01L27/0255

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC分类号： H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC分类号： H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

摘要： An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US20240088134A1

公开(公告)日：2024-03-14

申请号：US17943815

申请日：2022-09-13

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinsky

IPC分类号： H01L27/02 ,  H01L21/8234

CPC分类号： H01L27/0266 ,  H01L21/823418 ,  H01L21/823481

摘要： An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.

公开(公告)号：US20240088133A1

公开(公告)日：2024-03-14

申请号：US17943840

申请日：2022-09-13

申请人： INTEL CORPORATION

发明人： Nicholas A. Thomson ,  Ayan Kar ,  Kalyan C. Kolluru ,  Mauro J. Kobrinksy ,  Benjamin Orr

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L23/5283 ,  H01L27/0266 ,  H01L29/0673 ,  H01L29/8611

摘要： An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.