公开(公告)号：US20180364792A1

公开(公告)日：2018-12-20

申请号：US15984185

申请日：2018-05-18

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D10/171

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US10768680B2

公开(公告)日：2020-09-08

申请号：US15678025

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/00 ,  G06F1/3206 ,  G06F9/30 ,  G06F1/3287 ,  G06F9/52 ,  G06F1/3203

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US20230004209A1

公开(公告)日：2023-01-05

申请号：US17879635

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US09733689B2

公开(公告)日：2017-08-15

申请号：US14752896

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/30 ,  G06F9/52

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/52 ,  Y02D10/171

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US10564705B2

公开(公告)日：2020-02-18

申请号：US15984185

申请日：2018-05-18

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe Fiat ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US10007323B2

公开(公告)日：2018-06-26

申请号：US14139864

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe Fiat ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D10/171

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US11422615B2

公开(公告)日：2022-08-23

申请号：US16741215

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe Fiat ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US20200272219A1

公开(公告)日：2020-08-27

申请号：US16741215

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Vishwesh M. Rudramuni ,  Richard Quinzio ,  Christophe FIAT ,  Aymen Zayet ,  Youvedeep Singh ,  Illyas M. Mansoor

IPC: G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

公开(公告)号：US20180059766A1

公开(公告)日：2018-03-01

申请号：US15678025

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/32 ,  G06F9/52 ,  G06F9/30

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.