公开(公告)号：US10148278B2

公开(公告)日：2018-12-04

申请号：US15863487

申请日：2018-01-05

Applicant: Intel IP Corporation

Inventor： Marco Bresciani ,  John G. Kauffman ,  Udo Schuetz ,  Patrick Torta ,  Francesco Conzatti

IPC: H03M1/00 ,  H03M1/10 ,  H03M3/00 ,  H03M1/46

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

公开(公告)号：US20180183452A1

公开(公告)日：2018-06-28

申请号：US15863487

申请日：2018-01-05

Applicant: Intel IP Corporation

Inventor： Marco Bresciani ,  John G. Kauffman ,  Udo Schuetz ,  Patrick Torta ,  Francesco Conzatti

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/46 ,  H03M3/386 ,  H03M3/424 ,  H03M3/454 ,  H03M3/464

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

公开(公告)号：US09866227B1

公开(公告)日：2018-01-09

申请号：US15391599

申请日：2016-12-27

Applicant: Intel IP Corporation

Inventor： Marco Bresciani ,  John G. Kauffman ,  Udo Schuetz ,  Patrick Torta ,  Francesco Conzatti

IPC: H03M1/00 ,  H03M1/10 ,  H03M1/46 ,  H03M3/00

CPC classification number: H03M1/1009 ,  H03M1/46 ,  H03M3/386 ,  H03M3/424 ,  H03M3/454 ,  H03M3/464

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.