公开(公告)号：US20160248612A1

公开(公告)日：2016-08-25

申请号：US14993157

申请日：2016-01-12

Applicant: Intel IP Corporation

Inventor： Thomas Esch ,  Edgar Bolinth ,  Markus Jordan ,  Tobias Scholand ,  Michael Speth

IPC: H04L25/06 ,  H04J3/06

CPC classification number: H04L25/06 ,  H04B1/7107 ,  H04J3/0602 ,  H04J13/004 ,  H04L27/3818

Abstract: A method (200) of bias cancellation for a radio channel sequence includes: receiving (201) a radio signal, the radio signal comprising a radio channel sequence coded by a first signature, the first signature belonging to a set of orthogonal signatures; decoding (202) the radio channel sequence based on the first signature to generate a decoded radio channel sequence; decoding (203) the radio channel sequence based on a second signature, wherein the second signature is orthogonal to the signatures of the set of orthogonal signatures, to generate a bias of the radio channel sequence; and canceling (204) the bias of the radio channel sequence from the decoded radio channel sequence.

Abstract translation: 一种用于无线电信道序列的偏置消除的方法（200）包括：接收（201）无线电信号，所述无线电信号包括由第一签名编码的无线电信道序列，所述第一签名属于一组正交签名; 基于所述第一签名解码（202）所述无线电信道序列以生成解码的无线电信道序列; 基于第二签名解码（203）所述无线电信道序列，其中所述第二签名与所述正交签名集合的签名正交，以产生所述无线电信道序列的偏差; 并从解码的无线电信道序列中取消（204）无线信道序列的偏置。

公开(公告)号：US09974024B2

公开(公告)日：2018-05-15

申请号：US15077197

申请日：2016-03-22

Applicant: Intel IP Corporation

Inventor： Michael Speth ,  Armin Haeutle ,  Frank Huertgen ,  Biswajit Dey ,  Markus Jordan

IPC: H04W52/02

CPC classification number: H04W52/0245 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1262

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

公开(公告)号：US10405171B2

公开(公告)日：2019-09-03

申请号：US15758740

申请日：2016-08-24

Applicant: Intel IP Corporation

Inventor： Herbert Dawid ,  Tobias Scholand ,  Michael Speth ,  Roland Hellfajer ,  Markus Jordan ,  Edgar Bolinth

IPC: H04W8/18 ,  H04W76/10 ,  H04W28/14 ,  H04W88/06 ,  H04W36/02 ,  H04W76/20 ,  H04W76/34 ,  H04W76/15

Abstract: A communication terminal is described with a controller configured to receive, from applications, respective requests for an exchange of application layer data over a communication network associated with the respective application, to select a first application, to control a communication circuit to perform an exchange according to the request received from the first application, to initiate, for a second application, a buffering of application layer data requested to be exchanged according to the request received from the second application, to control the communication circuit to release the first network layer communication connection based on a duration of the buffering and to establish a second network layer communication connection to a communication network associated with the second application and perform an exchange according to the request received from the second application over the second network layer communication connection after release of the first network layer communication connection.

公开(公告)号：US20180337804A1

公开(公告)日：2018-11-22

申请号：US15777537

申请日：2016-11-09

Applicant: Intel IP Corporation

Inventor： Thomas Esch ,  Mihail Petrov ,  Tobias Scholand ,  Michael Speth ,  Norbert Neurohr

IPC: H04L25/03 ,  H04L25/02 ,  H04B1/7105

CPC classification number: H04L25/0212 ,  H04L25/022 ,  H04L25/03133

Abstract: An equalizer includes: a channel estimator configured to generate a set of time-domain channel coefficients based on a receive signal; a frequency-domain transformer configured to generate a set of frequency-domain channel coefficients based on a frequency transform of the set of time-domain channel coefficients; an equalizer coefficient generator configured to generate a set of frequency-domain equalizer coefficients based on the set of frequency-domain channel coefficients; a time-domain transformer configured to generate a set of time-domain equalizer coefficients based on a time transform of the set of frequency-domain equalizer coefficients; and a filter configured to filter the receive signal based on a filter function that is based on the set of time-domain equalizer coefficients.

公开(公告)号：US10044533B2

公开(公告)日：2018-08-07

申请号：US14993157

申请日：2016-01-12

Applicant: Intel IP Corporation

Inventor： Thomas Esch ,  Edgar Bolinth ,  Markus Jordan ,  Tobias Scholand ,  Michael Speth

IPC: H04L25/06 ,  H04L27/38 ,  H04B1/7107 ,  H04J13/00 ,  H04J3/06

Abstract: A method (200) of bias cancellation for a radio channel sequence includes: receiving (201) a radio signal, the radio signal comprising a radio channel sequence coded by a first signature, the first signature belonging to a set of orthogonal signatures; decoding (202) the radio channel sequence based on the first signature to generate a decoded radio channel sequence; decoding (203) the radio channel sequence based on a second signature, wherein the second signature is orthogonal to the signatures of the set of orthogonal signatures, to generate a bias of the radio channel sequence; and canceling (204) the bias of the radio channel sequence from the decoded radio channel sequence.

公开(公告)号：US20160316434A1

公开(公告)日：2016-10-27

申请号：US15077197

申请日：2016-03-22

Applicant: Intel IP Corporation

Inventor： Michael Speth ,  Armin Haeutle ,  Frank Huertgen ,  Biswajit Dey ,  Markus Jordan

IPC: H04W52/02 ,  H04W24/08

CPC classification number: H04W52/0245 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1262

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

Abstract translation: 根据示例的电路包括被配置为接收包括数据流的信号的接收器电路，所述数据流包括至少一个数据块，所述至少一个数据块的块包括至少两个子块， 所述块的有效载荷被冗余地编码在所述至少两个子块中，并且所述块的所述至少两个子块在所述块内随时间一致地排列。 该电路还包括控制电路，该控制电路被配置为当满足该允许条件时，在该块的至少两个子块中的至少一个子块的至少一部分期间将接收器电路切换为不准备接收状态 。