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公开(公告)号：US11816034B2
公开(公告)日：2023-11-14
申请号：US17079619
申请日：2020-10-26
发明人： Mohit Karve , Naga P. Gorti
IPC分类号： G06F12/0862
CPC分类号： G06F12/0862 , G06F2212/602
摘要： A Bloom filter is used to track contents of a cache. A system checks the Bloom filter before deciding whether to prefetch an address (by hashing the address and checking a value of the Bloom filter at an index based on the hash). This allows the system to utilize more aggressive prefetching schemes by reducing the risk of wasteful redundant prefetch operations.
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公开(公告)号：US11182161B2
公开(公告)日：2021-11-23
申请号：US16849001
申请日：2020-04-15
发明人： Mohit Karve , Edmund Joseph Gieske , Naga P. Gorti
摘要： An information handling system includes a memory subsystem; a processor; and a link connecting the processor and memory subsystem, the processor having a memory controller to manage load instructions; a data cache to hold data for use by the processor; a load store unit to execute load instructions; an instruction fetch unit to fetch load instructions and a cache line utility tracker (CUT) table having a plurality of entries, each entry having a utility field to indicate the portions of a cache line of the load instruction that were used by the processor. The system configured to: determine whether the load instruction is in the CUT Table and in response determine from the CUT Table whether to request a partial cache line; and in response to the data not being in the data cache, transmit a memory request for a partial cache line.
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公开(公告)号：US11586440B2
公开(公告)日：2023-02-21
申请号：US17336240
申请日：2021-06-01
发明人： Naga P. Gorti , Mohit Karve
摘要： A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.
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公开(公告)号：US11561796B2
公开(公告)日：2023-01-24
申请号：US16929208
申请日：2020-07-15
发明人： Naga P. Gorti , Mohit Karve
IPC分类号： G06F9/38 , G06F12/08 , G06F12/0862 , G06F12/0875
摘要： A computer-implemented method to prefetch non-sequential instruction addresses (I/A) includes, determining, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's. The method further includes storing the first I/A in a linked miss-to-miss (LMTM) table. The method also includes determining a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's. The method includes linking, in the LMTM table, the second miss to the first miss. The method also includes prefetching, in response to a third access attempt of the first I/A, the second I/A in the cache.
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公开(公告)号：US11526360B2
公开(公告)日：2022-12-13
申请号：US16196151
申请日：2018-11-20
发明人： Naga P. Gorti , Dave S. Levitan
IPC分类号： G06F9/38
摘要： A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction prediction outcome, and the branch prediction unit. The branch predictor is turned off to save power and avoid miss-predictions when the branch predictor and/or branch prediction unit accuracy is lower than expected.
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公开(公告)号：US20240202127A1
公开(公告)日：2024-06-20
申请号：US18066480
申请日：2022-12-15
发明人： Bryan Lloyd , David A. Hrusecky , Richard J. Eickemeyer , Mohit Karve , Dung Q. Nguyen , Nicholas R. Orzol , Sheldon Bernard Levenstein , Naga P. Gorti
IPC分类号： G06F12/0875 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0875 , G06F9/30043 , G06F9/3802 , G06F2212/452
摘要： Embodiments relate to sideband instruction address translation. According to an aspect, a computer-implemented method includes managing, within a processor, an instruction effective-to-real-address table (I-ERAT) separate from a main ERAT, where the I-ERAT has a smaller storage capacity than the main ERAT. The method also includes indicating an I-ERAT hit based on determining that an instruction address for an instruction cache is stored in the I-ERAT, bypassing an arbitrator within the processor and sending a translated address from the I-ERAT to the instruction cache based on detecting the I-ERAT hit, and sending an address translation request through the arbitrator to the main ERAT based on an I-ERAT miss and writing a translation result of the main ERAT to the I-ERAT.
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公开(公告)号：US11822922B2
公开(公告)日：2023-11-21
申请号：US17566744
申请日：2021-12-31
发明人： Mohit Karve , Naga P. Gorti
IPC分类号： G06F9/38 , G06F12/08 , G06F12/0862
CPC分类号： G06F9/3802 , G06F12/0862 , G06F2212/602
摘要： A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.
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公开(公告)号：US11416257B2
公开(公告)日：2022-08-16
申请号：US16380737
申请日：2019-04-10
摘要： Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.
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公开(公告)号：US20220129385A1
公开(公告)日：2022-04-28
申请号：US17079619
申请日：2020-10-26
发明人： Mohit Karve , Naga P. Gorti
IPC分类号： G06F12/0862
摘要： A Bloom filter is used to track contents of a cache. A system checks the Bloom filter before deciding whether to prefetch an address (by hashing the address and checking a value of the Bloom filter at an index based on the hash). This allows the system to utilize more aggressive prefetching schemes by reducing the risk of wasteful redundant prefetch operations.
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公开(公告)号：US20220019440A1
公开(公告)日：2022-01-20
申请号：US16929208
申请日：2020-07-15
发明人： Naga P. Gorti , Mohit Karve
IPC分类号： G06F9/38
摘要： A computer-implemented method to prefetch non-sequential instruction addresses (I/A) includes, determining, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's. The method further includes storing the first I/A in a linked miss-to-miss (LMTM) table. The method also includes determining a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's. The method includes linking, in the LMTM table, the second miss to the first miss. The method also includes prefetching, in response to a third access attempt of the first I/A, the second I/A in the cache.
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