利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.026 秒)

    Phase jumping locked loop circuit
    3.
    发明授权
    Phase jumping locked loop circuit 有权
    相跳锁定回路电路

    公开(公告)号：US07135903B2

    公开(公告)日：2006-11-14

    申请号：US10374251

    申请日：2003-02-25

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    摘要： A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

    摘要翻译： 一个跳相锁定环路。 锁定环电路包括多个差分放大器和可切换地耦合到每个差分放大器的偏置电路。 每个差分放大器具有输入以接收耦合到公共输出信号线对的相应的一对时钟信号和输出。 偏置电路包括彼此并联并与第一组差分放大器串联耦合的第一多个偏置晶体管，以及第二组多个偏置晶体管，其彼此并联耦合并与第二组 差分放大器。

    Method and apparatus for digital duty cycle adjustment
    5.
    发明授权
    Method and apparatus for digital duty cycle adjustment 失效
    用于数字占空比调整的方法和装置

    公开(公告)号：US06967514B2

    公开(公告)日：2005-11-22

    申请号：US10277738

    申请日：2002-10-21

    申请人： Jade M. Kizer ,  Roxanne T. Vu

    发明人： Jade M. Kizer ,  Roxanne T. Vu

    IPC分类号： H03K5/00 ,  H03K5/156 ,  H03K19/003 ,  H03K3/17

    CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00208

    摘要： Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.

    摘要翻译： 调整时钟占空比。 响应于时钟信号产生增量误差信号。 响应于增量误差信号产生累积误差信号。 复位增量误差信号，并根据累积误差信号调整时钟信号的占空比。

    System with phase jumping locked loop circuit
    7.
    发明授权
    System with phase jumping locked loop circuit 有权
    具有相跳锁定环路的系统

    公开(公告)号：US06759881B2

    公开(公告)日：2004-07-06

    申请号：US10374390

    申请日：2003-02-25

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Craig E. Hampel

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Craig E. Hampel

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    摘要： An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

    摘要翻译： 一种具有选择电路，加法电路和相位混频器的集成电路装置。 选择电路选择多个偏移值中的一个作为选择的偏移。 求和电路将所选择的偏移与相位计数值相加，相位计数值指示参考时钟信号和第一多个时钟信号之间的相位差。 相位混频器根据所选择的偏移和相位计数值的和来组合第一多个时钟信号以产生输出时钟信号。

    Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback
    8.
    发明授权
    Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback 失效
    具有响应于反馈的电压驱动器进行分布式电压补偿的方法和装置

    公开(公告)号：US07046078B2

    公开(公告)日：2006-05-16

    申请号：US11126643

    申请日：2005-05-11

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Adam Chuen-Huei Chou ,  Roxanne T. Vu

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Adam Chuen-Huei Chou ,  Roxanne T. Vu

    IPC分类号： G05F1/10

    CPC分类号： G06F1/26

    摘要： An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

    摘要翻译： 集成电路具有参考分布式参考电压工作的一个或多个组件。 参考电压驱动器产生补偿的参考电压，并且补偿的参考电压被分配以在组件处形成分布式参考电压。 由于迹线电阻和栅极泄漏等因素，分布式参考电压相对于补偿参考电压降低。 参考电压驱动器响应于从分布式参考电压得到的反馈，以调整补偿的参考电压，使得分布式参考电压近似等于标称参考电压。

    Differential amplifiers with current and resistance compensation elements for balanced output
    9.
    发明授权
    Differential amplifiers with current and resistance compensation elements for balanced output 失效
    具有电流和电阻补偿元件的差分放大器，用于平衡输出

    公开(公告)号：US06369652B1

    公开(公告)日：2002-04-09

    申请号：US09571089

    申请日：2000-05-15

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Roxanne T. Vu

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Roxanne T. Vu

    IPC分类号： H03F345

    CPC分类号： H03F3/45766 ,  H03F3/45183 ,  H03F2203/45471 ,  H03F2203/45686 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03K5/2481 ,  H03L7/0812

    摘要： A differential amplifier has unequal resistance in its legs that compensates for an unequal current flow through the legs during a logic zero data input compared to logic one data input. The unequal resistance may be provided by adding a resistor in parallel to the leg that carries greater current during amplification, lowering the resistance in that leg and also the voltage that is output from that leg. Alternatively, a variable resistance may be provided to at least one of the legs to compensate for current inequalities between the legs. The variable resistance may be provided by a transistor that is controlled by a signal indicating process, voltage and/or temperature conditions of the amplifier and adjacent circuitry. Transistors may be employed in both legs as well as in a current source for the amplifier, providing balanced current regulation for the amplifier. Such current compensated differential amplifiers may be employed for various functions, for example as input receivers or delay elements in high frequency memory systems.

    摘要翻译： 与逻辑1数据输入相比，差分放大器在其逻辑零数据输入期间，其腿部具有不相等的电阻，其补偿与逻辑零数据输入中不平衡的电流。 可以通过在放大期间增加一个并联的电阻器来提供不平等的电阻，该电阻器在放大期间承载更大的电流，降低该支路中的电阻以及从该支路输出的电压。 或者，可以向至少一个腿提供可变电阻以补偿腿之间的当前不平等。 可变电阻可以由由指示放大器和相邻电路的处理，电压和/或温度条件的信号控制的晶体管提供。 晶体管可以用于两个支路以及用于放大器的电流源，为放大器提供平衡的电流调节。 这种电流补偿差分放大器可用于各种功能，例如作为高频存储器系统中的输入接收器或延迟元件。