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55 条记录 (耗时 0.032 秒)

    Phase jumping locked loop circuit
    1.
    发明授权
    Phase jumping locked loop circuit 有权
    相跳锁定回路电路

    公开(公告)号：US07135903B2

    公开(公告)日：2006-11-14

    申请号：US10374251

    申请日：2003-02-25

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    摘要： A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

    摘要翻译： 一个跳相锁定环路。 锁定环电路包括多个差分放大器和可切换地耦合到每个差分放大器的偏置电路。 每个差分放大器具有输入以接收耦合到公共输出信号线对的相应的一对时钟信号和输出。 偏置电路包括彼此并联并与第一组差分放大器串联耦合的第一多个偏置晶体管，以及第二组多个偏置晶体管，其彼此并联耦合并与第二组 差分放大器。

    Phase synchronization for wide area integrated circuits
    6.
    发明授权
    Phase synchronization for wide area integrated circuits 有权
    广域集成电路的相位同步

    公开(公告)号：US07161400B2

    公开(公告)日：2007-01-09

    申请号：US10963698

    申请日：2004-10-13

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    IPC分类号： H03L7/06

    CPC分类号： G06F1/10 ,  G06F1/12 ,  H03L7/00

    摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

    摘要翻译： 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

    Phase synchronization for wide area integrated circuits
    7.
    发明授权
    Phase synchronization for wide area integrated circuits 有权
    广域集成电路的相位同步

    公开(公告)号：US07932755B2

    公开(公告)日：2011-04-26

    申请号：US11620309

    申请日：2007-01-05

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Leung Yu ,  Jade M. Kizer

    IPC分类号： H03L7/06

    CPC分类号： G06F1/10 ,  G06F1/12 ,  H03L7/00

    摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

    摘要翻译： 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

    System with phase jumping locked loop circuit
    9.
    发明授权
    System with phase jumping locked loop circuit 有权
    具有相跳锁定环路的系统

    公开(公告)号：US06759881B2

    公开(公告)日：2004-07-06

    申请号：US10374390

    申请日：2003-02-25

    申请人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Craig E. Hampel

    发明人： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Craig E. Hampel

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    摘要： An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

    摘要翻译： 一种具有选择电路，加法电路和相位混频器的集成电路装置。 选择电路选择多个偏移值中的一个作为选择的偏移。 求和电路将所选择的偏移与相位计数值相加，相位计数值指示参考时钟信号和第一多个时钟信号之间的相位差。 相位混频器根据所选择的偏移和相位计数值的和来组合第一多个时钟信号以产生输出时钟信号。

    Method and apparatus for digital duty cycle adjustment
    10.
    发明授权
    Method and apparatus for digital duty cycle adjustment 失效
    用于数字占空比调整的方法和装置

    公开(公告)号：US06967514B2

    公开(公告)日：2005-11-22

    申请号：US10277738

    申请日：2002-10-21

    申请人： Jade M. Kizer ,  Roxanne T. Vu

    发明人： Jade M. Kizer ,  Roxanne T. Vu

    IPC分类号： H03K5/00 ,  H03K5/156 ,  H03K19/003 ,  H03K3/17

    CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00208

    摘要： Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.

    摘要翻译： 调整时钟占空比。 响应于时钟信号产生增量误差信号。 响应于增量误差信号产生累积误差信号。 复位增量误差信号，并根据累积误差信号调整时钟信号的占空比。