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    Signal lines with internal and external termination
    2.
    发明授权
    Signal lines with internal and external termination 有权
    具有内部和外部端接的信号线

    公开(公告)号：US08692573B2

    公开(公告)日：2014-04-08

    申请号：US13316046

    申请日：2011-12-09

    Applicant: Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    Inventor： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

    Abstract translation: 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

    Signal lines with internal and external termination
    4.
    发明授权
    Signal lines with internal and external termination 有权
    具有内部和外部端接的信号线

    公开(公告)号：US08130010B2

    公开(公告)日：2012-03-06

    申请号：US13022539

    申请日：2011-02-07

    Applicant: Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    Inventor： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

    Abstract translation: 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，内部阻抗可以使用无源部件，有源部件或两者来实现。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

    Signal lines with internal and external termination
    5.
    发明授权
    Signal lines with internal and external termination 有权
    具有内部和外部端接的信号线

    公开(公告)号：US07915912B2

    公开(公告)日：2011-03-29

    申请号：US12555886

    申请日：2009-09-09

    Applicant: Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    Inventor： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

    Abstract translation: 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

    Driver calibration methods and circuits
    6.
    发明授权
    Driver calibration methods and circuits 有权
    驱动器校准方法和电路

    公开(公告)号：US07808278B2

    公开(公告)日：2010-10-05

    申请号：US12151614

    申请日：2008-05-07

    Applicant: Huy M. Nguyen ,  Vijay Gadde ,  Sivakumar Doriaswamy

    Inventor： Huy M. Nguyen ,  Vijay Gadde ,  Sivakumar Doriaswamy

    IPC: H03K19/094

    CPC classification number: H04L25/028 ,  H03F3/19 ,  H03K19/0005 ,  H03K19/00384

    Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

    Abstract translation: 描述了通过校准的驱动强度和终端阻抗促进高速通信的放大器。 驱动器和终端元件可以被划分为数个N个并行部分，其中一个或多个可被禁用和更新，而不会干扰信号（例如，时钟或数据）传输。 一些实施例通过检查输入信号来识别非活动元件。

    Phase jumping locked loop circuit
    8.
    发明授权
    Phase jumping locked loop circuit 有权
    相跳锁定回路电路

    公开(公告)号：US07135903B2

    公开(公告)日：2006-11-14

    申请号：US10374251

    申请日：2003-02-25

    Applicant: Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    Inventor： Jade M. Kizer ,  Benedict C. Lau ,  Roxanne T. Vu ,  Huy M. Nguyen ,  Leung Yu ,  Adam Chuen-Huei Chou

    IPC: H03L7/06

    CPC classification number: H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

    Abstract: A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

    Abstract translation: 一个跳相锁定环路。 锁定环电路包括多个差分放大器和可切换地耦合到每个差分放大器的偏置电路。 每个差分放大器具有输入以接收耦合到公共输出信号线对的相应的一对时钟信号和输出。 偏置电路包括彼此并联并与第一组差分放大器串联耦合的第一多个偏置晶体管，以及第二组多个偏置晶体管，其彼此并联耦合并与第二组 差分放大器。

    Method and apparatus for low capacitance, high output impedance driver
    10.
    发明授权
    Method and apparatus for low capacitance, high output impedance driver 失效
    低电容，高输出阻抗驱动器的方法和装置

    公开(公告)号：US06330193B1

    公开(公告)日：2001-12-11

    申请号：US09539807

    申请日：2000-03-31

    Applicant: Leung Yu ,  Roxanne T. Vu ,  Benedict C. Lau ,  Huy M. Nguyen ,  James A. Gasbarro

    Inventor： Leung Yu ,  Roxanne T. Vu ,  Benedict C. Lau ,  Huy M. Nguyen ,  James A. Gasbarro

    IPC: G11C700

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1084

    Abstract: A method is described that compares two voltages, one of the voltages indicative of a data line voltage, a second of the voltages indicative of a reference voltage. An input signal is sent to each of a plurality of drivers where at least one of the drivers is coupled to the data line. The input signal is based upon the comparison. A bias is applied to a transistor from the input signal, the bias keeping the transistor in a high output impedance state when the two voltages are the same.

    Abstract translation: 描述了一种方法，其比较两个电压，指示数据线电压的电压之一，表示参考电压的第二电压。 输入信号被发送到多个驱动器中的至少一个驱动器耦合到数据线的每个驱动器。 输入信号基于比较。 从输入信号向晶体管施加偏压，当两个电压相同时，偏置保持晶体管处于高输出阻抗状态。

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