Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality
    1.
    发明授权
    Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality 有权
    基于接收机侧链路质量评估的动态分集装置和方法

    公开(公告)号:US07610019B2

    公开(公告)日:2009-10-27

    申请号:US11449068

    申请日:2006-06-08

    IPC分类号: H04B17/00

    摘要: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

    摘要翻译: 基于接收机侧链路质量评估的用于动态分集信号接收的装置包括两个或更多个天线。 至少一个开关连接到两个或更多个天线。 动态分集控制器连接到至少一个开关。 动态分集控制器包括链路质量评估者,以评估链路质量并生成链路特征值。 响应于链路特征值的分集配置选择器选择性地激活至少一个交换机以实现动态分集配置。 链路质量评估器包括信号强度分析器,调制解调器检测器和/或MAC层分析器,以评估所接收的信号并产生链路表征值。

    Method and apparatus for implementing maximum transition run codes
    4.
    发明授权
    Method and apparatus for implementing maximum transition run codes 失效
    实现最大过渡运行代码的方法和装置

    公开(公告)号:US5859601A

    公开(公告)日:1999-01-12

    申请号:US730716

    申请日:1996-10-15

    摘要: Apparatus and method for coding to improve the minimum distance properties of sequence detectors operating at high densities in storage systems is presented. The coding scheme of the present invention is referred to as maximum transition run (MTR) code and eliminates data patterns producing long runs of consecutive transitions while imposing the usual k constraint necessary for timing recovery. The code has a distance gaining property similar to an existing (1,k) runlength-limited (RLL) code, but can be implemented with considerably higher code rates. When the MTR code is used with fixed delay tree search (FDTS) or high order partial response maximum likelihood (PRML) detectors, the bit error rate performance improves significantly over existing combinations of codes and detectors.

    摘要翻译: 提出了用于编码以提高在存储系统中以高密度运行的序列检测器的最小距离特性的装置和方法。 将本发明的编码方案称为最大转移运行(MTR)代码,并消除产生长时间连续转换的数据模式,同时施加定时恢复所需的常规k约束。 代码具有类似于现有(1,k)游程长度限制(RLL)代码的距离增益属性,但是可以以相当高的代码速率来实现。 当使用固定延迟树搜索(FDTS)或高阶部分响应最大似然(PRML)检测器的MTR代码时,与现有的代码和检测器组合相比,误码率性能显着提高。

    Method and apparatus for three dimensional sequence estimation in
partially constrained binary channels
    5.
    发明授权
    Method and apparatus for three dimensional sequence estimation in partially constrained binary channels 失效
    部分约束二进制信道中三维序列估计的方法和装置

    公开(公告)号:US5956195A

    公开(公告)日:1999-09-21

    申请号:US828497

    申请日:1997-03-31

    摘要: An information handling system, such as a magnetic disk drive, includes a data channel which has a method and apparatus for detecting binary symbols from a received signal subject to intersymbol interference and additive white Gaussian noise using a three dimensional observation space with orthogonal coordinate axes. Each of three consecutive synchronous observation samples of the received signal corresponding unambiguously to an axis in the observation space. A decision feedback equalizer removes intersymbol interference terms associated with prior detector outputs. A plurality of linear classifiers are used to partition the observation space. The second and/or third sample of the equivalent channel response is constrained relative to the first for the purpose of simplifying the linear classifiers. Boolean logic functions to decide into which decision region of the observation space a sample maps into. Incorporation of modulation coding constraints reduce the probability of error by increasing the Euclidean distance between symbols in the observation space. Symbol estimates are produced synchronously with a delay of two with respect to the current observation sample.

    摘要翻译: 诸如磁盘驱动器之类的信息处理系统包括数据通道,该数据通道具有使用具有正交坐标轴的三维观察空间的接收信号进行符号间干扰和加性白高斯噪声来检测二进制符号的方法和装置。 接收信号的三个连续同步观测样本中的每一个明确地对应于观测空间中的轴。 决策反馈均衡器去除与现有检测器输出相关联的符号间干扰项。 多个线性分类器用于分割观察空间。 为了简化线性分类器,等效信道响应的第二和/或第三样本相对于第一样本被约束。 布尔逻辑函数用于决定样本映射到的观测空间的决定区域。 调制编码约束的结合通过增加观察空间中的符号之间的欧氏距离来减小误差的概率。 符号估计与相对于当前观察样本的两个延迟同步产生。

    CCK demodulation via symbol decision feedback equalizer
    6.
    发明授权
    CCK demodulation via symbol decision feedback equalizer 有权
    通过符号判决反馈均衡器进行CCK解调

    公开(公告)号:US07526050B2

    公开(公告)日:2009-04-28

    申请号:US10460766

    申请日:2003-06-12

    IPC分类号: H03D1/00

    摘要: Demodulation techniques for a wireless communication system make use of a decision feedback equalization (DFE) technique to mitigate the effects of multipath channel characteristics on receiver performance. The techniques may be particularly useful in the demodulation of complementary code keying (CCK) symbols. A demodulator that performs such techniques may include a time-variant or time-invariant matched filter, a feedback intersymbol interference (ISI) canceller, a transform unit, a phase rotation estimator and corrector, a pattern-dependent bias canceller, and a maximum picker for symbol decisions. The transform unit may include a bank of correlators, or alternatively a fast Walsh transform unit.

    摘要翻译: 无线通信系统的解调技术利用判决反馈均衡(DFE)技术来减轻多径信道特性对接收机性能的影响。 这些技术在解码补码编码(CCK)符号中可能特别有用。 执行这种技术的解调器可以包括时变或时间不变的匹配滤波器,反馈符号间干扰(ISI)消除器,变换单元,相位旋转估计器和校正器,模式相关偏移消除器和最大选择器 用于符号决定。 变换单元可以包括一组相关器,或者可以包括快速沃尔什变换单元。

    Digital phase locked loop
    7.
    发明授权
    Digital phase locked loop 有权
    数字锁相环

    公开(公告)号:US07738600B2

    公开(公告)日:2010-06-15

    申请号:US11894102

    申请日:2007-08-20

    IPC分类号: H04L27/00 H03D3/24 H04L7/00

    摘要: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

    摘要翻译: 在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。 设备校正载波和采样相位误差以及相位相位噪声。 数字锁相环同时跟踪载波相位误差和采样相位误差,并校正频域中的信号。 该装置可以使用采样相位误差推进或延迟用于将来自时域的信号转换到频域的采样窗口。

    Digital front-end for wireless communication system
    8.
    发明授权
    Digital front-end for wireless communication system 有权
    数字前端无线通信系统

    公开(公告)号:US07190748B2

    公开(公告)日:2007-03-13

    申请号:US10144445

    申请日:2002-05-10

    IPC分类号: H04L27/08 H04L1/02 H04B7/10

    摘要: A digital front-end for a wireless communication system incorporates gain control, signal detection, frame synchronization and carrier frequency offset (CFO) estimation and correction features configured for use with multiple receive antennas. The digital front-end may be applied to a wireless communication system in which transmitted signals carry a repeated signal pattern, such as orthogonal frequency division multiplexing (OFDM) systems. An example of a repeated signal pattern is the preamble of a signal transmitted according to the IEEE 802.11a wireless local area network (WLAN) standard. The signal detection, frame synchronization, and CFO estimation techniques make use of signals received from multiple antenna paths to provide enhanced performance. The gain control feature may be configured to adjust the gain in steps. The frame synchronization technique may operate as a function of gain control, handling the input signal differently before and after gain adjustment.

    摘要翻译: 用于无线通信系统的数字前端包括配置为与多个接收天线一起使用的增益控制,信号检测,帧同步和载波频率偏移(CFO)估计和校正特征。 数字前端可以应用于其中发送的信号携带重复信号模式的无线通信系统,例如正交频分复用(OFDM)系统。 重复信号模式的示例是根据IEEE 802.11a无线局域网(WLAN)标准发送的信号的前导码。 信号检测,帧同步和CFO估计技术利用从多个天线路径接收的信号来提供增强的性能。 增益控制功能可以被配置为逐步调整增益。 帧同步技术可以作为增益控制的功能来操作,在增益调整之前和之后处理输入信号不同。

    Digital phase locked loop
    10.
    发明申请
    Digital phase locked loop 有权
    数字锁相环

    公开(公告)号:US20070286268A1

    公开(公告)日:2007-12-13

    申请号:US11894102

    申请日:2007-08-20

    IPC分类号: H04B3/46

    摘要: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

    摘要翻译: 在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。 设备校正载波和采样相位误差以及相位相位噪声。 数字锁相环同时跟踪载波相位误差和采样相位误差,并校正频域中的信号。 该装置可以使用采样相位误差推进或延迟用于将来自时域的信号转换到频域的采样窗口。