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    Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality
    1.
    发明授权
    Apparatus and method for dynamic diversity based upon receiver-side assessment of link quality 有权
    基于接收机侧链路质量评估的动态分集装置和方法

    公开(公告)号：US07610019B2

    公开(公告)日：2009-10-27

    申请号：US11449068

    申请日：2006-06-08

    申请人： Jaekyun Moon ,  Younggyun Kim ,  Barrett J. Brickner ,  Paul C. Edwards ,  Michael E. Butenhoff

    发明人： Jaekyun Moon ,  Younggyun Kim ,  Barrett J. Brickner ,  Paul C. Edwards ,  Michael E. Butenhoff

    IPC分类号： H04B17/00

    CPC分类号： H04L1/0001 ,  H04B7/0811 ,  H04B7/0814 ,  H04L1/0015 ,  H04L1/206

    摘要： An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

    摘要翻译： 基于接收机侧链路质量评估的用于动态分集信号接收的装置包括两个或更多个天线。 至少一个开关连接到两个或更多个天线。 动态分集控制器连接到至少一个开关。 动态分集控制器包括链路质量评估者，以评估链路质量并生成链路特征值。 响应于链路特征值的分集配置选择器选择性地激活至少一个交换机以实现动态分集配置。 链路质量评估器包括信号强度分析器，调制解调器检测器和/或MAC层分析器，以评估所接收的信号并产生链路表征值。

    CCK demodulation via symbol decision feedback equalizer
    4.
    发明授权
    CCK demodulation via symbol decision feedback equalizer 有权
    通过符号判决反馈均衡器进行CCK解调

    公开(公告)号：US07526050B2

    公开(公告)日：2009-04-28

    申请号：US10460766

    申请日：2003-06-12

    申请人： Younggyun Kim ,  Jaekyun Moon

    发明人： Younggyun Kim ,  Jaekyun Moon

    IPC分类号： H03D1/00

    CPC分类号： H04B1/71057 ,  H04B1/7093 ,  H04B2201/709709 ,  H04J11/0033 ,  H04L23/02 ,  H04L25/03057 ,  H04L25/03267 ,  H04L2025/03375 ,  H04L2025/03503 ,  H04L2027/0042

    摘要： Demodulation techniques for a wireless communication system make use of a decision feedback equalization (DFE) technique to mitigate the effects of multipath channel characteristics on receiver performance. The techniques may be particularly useful in the demodulation of complementary code keying (CCK) symbols. A demodulator that performs such techniques may include a time-variant or time-invariant matched filter, a feedback intersymbol interference (ISI) canceller, a transform unit, a phase rotation estimator and corrector, a pattern-dependent bias canceller, and a maximum picker for symbol decisions. The transform unit may include a bank of correlators, or alternatively a fast Walsh transform unit.

    摘要翻译： 无线通信系统的解调技术利用判决反馈均衡（DFE）技术来减轻多径信道特性对接收机性能的影响。 这些技术在解码补码编码（CCK）符号中可能特别有用。 执行这种技术的解调器可以包括时变或时间不变的匹配滤波器，反馈符号间干扰（ISI）消除器，变换单元，相位旋转估计器和校正器，模式相关偏移消除器和最大选择器 用于符号决定。 变换单元可以包括一组相关器，或者可以包括快速沃尔什变换单元。

    Digital phase locked loop
    5.
    发明申请
    Digital phase locked loop 有权
    数字锁相环

    公开(公告)号：US20070286268A1

    公开(公告)日：2007-12-13

    申请号：US11894102

    申请日：2007-08-20

    申请人： Younggyun Kim ,  Jaekyun Moon

    发明人： Younggyun Kim ,  Jaekyun Moon

    IPC分类号： H04B3/46

    CPC分类号： H04L27/2662 ,  H04L25/03159 ,  H04L27/2657 ,  H04L27/2676 ,  H04L2025/03414

    摘要： Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

    摘要翻译： 在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。 设备校正载波和采样相位误差以及相位相位噪声。 数字锁相环同时跟踪载波相位误差和采样相位误差，并校正频域中的信号。 该装置可以使用采样相位误差推进或延迟用于将来自时域的信号转换到频域的采样窗口。

    Digital phase locked loop
    6.
    发明授权
    Digital phase locked loop 有权
    数字锁相环

    公开(公告)号：US07738600B2

    公开(公告)日：2010-06-15

    申请号：US11894102

    申请日：2007-08-20

    申请人： Younggyun Kim ,  Jaekyun Moon

    发明人： Younggyun Kim ,  Jaekyun Moon

    IPC分类号： H04L27/00 ,  H03D3/24 ,  H04L7/00

    CPC分类号： H04L27/2662 ,  H04L25/03159 ,  H04L27/2657 ,  H04L27/2676 ,  H04L2025/03414

    摘要： Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

    摘要翻译： 在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。 设备校正载波和采样相位误差以及相位相位噪声。 数字锁相环同时跟踪载波相位误差和采样相位误差，并校正频域中的信号。 该装置可以使用采样相位误差推进或延迟用于将来自时域的信号转换到频域的采样窗口。

    Digital front-end for wireless communication system
    7.
    发明授权
    Digital front-end for wireless communication system 有权
    数字前端无线通信系统

    公开(公告)号：US07190748B2

    公开(公告)日：2007-03-13

    申请号：US10144445

    申请日：2002-05-10

    申请人： Younggyun Kim ,  Jaekyun Moon

    发明人： Younggyun Kim ,  Jaekyun Moon

    IPC分类号： H04L27/08 ,  H04L1/02 ,  H04B7/10

    CPC分类号： H04W28/18 ,  H04B7/0848 ,  H04B7/0854 ,  H04B7/0857 ,  H04L1/06 ,  H04L27/2657 ,  H04L27/2662 ,  H04L27/2675 ,  H04W56/00 ,  H04W84/12

    摘要： A digital front-end for a wireless communication system incorporates gain control, signal detection, frame synchronization and carrier frequency offset (CFO) estimation and correction features configured for use with multiple receive antennas. The digital front-end may be applied to a wireless communication system in which transmitted signals carry a repeated signal pattern, such as orthogonal frequency division multiplexing (OFDM) systems. An example of a repeated signal pattern is the preamble of a signal transmitted according to the IEEE 802.11a wireless local area network (WLAN) standard. The signal detection, frame synchronization, and CFO estimation techniques make use of signals received from multiple antenna paths to provide enhanced performance. The gain control feature may be configured to adjust the gain in steps. The frame synchronization technique may operate as a function of gain control, handling the input signal differently before and after gain adjustment.

    摘要翻译： 用于无线通信系统的数字前端包括配置为与多个接收天线一起使用的增益控制，信号检测，帧同步和载波频率偏移（CFO）估计和校正特征。 数字前端可以应用于其中发送的信号携带重复信号模式的无线通信系统，例如正交频分复用（OFDM）系统。 重复信号模式的示例是根据IEEE 802.11a无线局域网（WLAN）标准发送的信号的前导码。 信号检测，帧同步和CFO估计技术利用从多个天线路径接收的信号来提供增强的性能。 增益控制功能可以被配置为逐步调整增益。 帧同步技术可以作为增益控制的功能来操作，在增益调整之前和之后处理输入信号不同。

    Digital phase locked loop
    9.
    发明授权
    Digital phase locked loop 有权
    数字锁相环

    公开(公告)号：US07272175B2

    公开(公告)日：2007-09-18

    申请号：US10137986

    申请日：2002-05-01

    申请人： Younggyun Kim ,  Jaekyun Moon

    发明人： Younggyun Kim ,  Jaekyun Moon

    IPC分类号： H04L27/14

    CPC分类号： H04L27/2662 ,  H04L25/03159 ,  H04L27/2657 ,  H04L27/2676 ,  H04L2025/03414

    摘要： Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

    摘要翻译： 在该阶段编码信息的数字通信信号可能容易受到许多来源的相位误差的影响。 本发明校正载波和采样相位误差以及相位相位噪声。 数字锁相环同时跟踪载波相位误差和采样相位误差，并校正频域中的信号。 本发明可以使用采样相位误差来推进或延迟用于将来自时域的信号转换到频域的采样窗口。

    APPARATUS AND METHOD FOR UPDATING CHECK NODE OF LOW-DENSITY PARITY CHECK CODES
    10.
    发明申请
    APPARATUS AND METHOD FOR UPDATING CHECK NODE OF LOW-DENSITY PARITY CHECK CODES 审中-公开
    检查低密度奇偶校验码代码的装置和方法

    公开(公告)号：US20100037119A1

    公开(公告)日：2010-02-11

    申请号：US12517455

    申请日：2007-12-05

    申请人： Jong-Ee Oh ,  Yu-Ro Lee ,  Chanho Yoon ,  Minho Cheong ,  Sok-Kyu Lee ,  Yoo-Seung Song ,  Younggyun Kim

    发明人： Jong-Ee Oh ,  Yu-Ro Lee ,  Chanho Yoon ,  Minho Cheong ,  Sok-Kyu Lee ,  Yoo-Seung Song ,  Younggyun Kim

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6527 ,  H03M13/6544 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6583

    摘要： An apparatus and method for updating a check node of a low-density parity check (LDPC) code in order to decode the LDPC code are provided. The method includes the operations of: (a) obtaining a first bit of a first minimum value among input values, the number of input values being equal to the number of degrees of the check node, by performing an AND operation on first bits of the input values, the first bits being most significant bits of the input values; (b) obtaining result values by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values; and (c) performing operations (a) and (b) on the result values set as input values and performing operations (a) and (b) a number of times corresponding to the number of bits of each input value, that is, repeating until last bits are set as input values, to thereby obtain the first minimum value, the last bits being least significant bits of the input values. Accordingly, the complexity of hardware is reduced, and super high-speed processing is possible.

    摘要翻译： 提供了一种用于更新低密度奇偶校验（LDPC）码的校验节点以便解码LDPC码的装置和方法。 该方法包括以下操作：（a）通过对所述校验节点的第一比特执行“与”运算，获得输入值中的第一最小值的第一比特，输入值的数目等于校验节点的度数。 输入值，第一位是输入值的最高有效位; （b）通过对所述第一最小值的所述第一位和所述输入值的所述第一位中的每一个进行切换和顺序执行异或运算和或运算来获得结果值; 和（c）对设置为输入值的结果值执行操作（a）和（b），并且执行操作（a）和（b）与每个输入值的位数相对应的次数，即重复 直到最后的位被设置为输入值为止，从而获得第一最小值，最后的位是输入值的最低有效位。 因此，硬件的复杂度降低，超高速处理成为可能。