公开(公告)号：US20110032630A1

公开(公告)日：2011-02-10

申请号：US12536435

申请日：2009-08-05

申请人： Jaewook Lee ,  Sizhen Yang ,  Umang Mehta ,  Jerry Hodges ,  Marc Feller ,  Turguy Goker

发明人： Jaewook Lee ,  Sizhen Yang ,  Umang Mehta ,  Jerry Hodges ,  Marc Feller ,  Turguy Goker

IPC分类号： G11B20/20

CPC分类号： G11B20/10009 ,  G11B20/10027 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10074 ,  G11B20/10175 ,  G11B20/1024 ,  G11B20/10296 ,  G11B20/10351 ,  G11B20/10361 ,  G11B20/10425 ,  G11B20/10481 ,  G11B2220/90 ,  G11B2220/93

摘要： A circuit for a high-density data recording channel includes a first data detector, a second data detector, one or more multiplexers and a sequence identifier. The first data detector generates a first data detector output, and the second data detector generates a second data detector output. The multiplexers change between a first mode and a second mode to alternately receive the first data detector output and the second data detector output. The sequence identifier receives a data sequence including at least one of a first data sequence, such as VFO data, and a second data sequence, such as random data. The second data sequence includes a greater number of signal levels than the first data sequence. The sequence identifier changes the multiplexers between the first mode and the second mode based on whether the data sequence is the first data sequence or the second data sequence. The data sequence includes a plurality of timing stages. The sequence detector can at least partially control a loop bandwidth of the circuit based on the timing stage of the data sequence.

摘要翻译： 用于高密度数据记录通道的电路包括第一数据检测器，第二数据检测器，一个或多个多路复用器和序列标识符。 第一数据检测器产生第一数据检测器输出，第二数据检测器产生第二数据检测器输出。 复用器在第一模式和第二模式之间改变以交替地接收第一数据检测器输出和第二数据检测器输出。 序列标识符接收包括诸如VFO数据的第一数据序列和诸如随机数据的第二数据序列中的至少一个的数据序列。 第二数据序列包括比第一数据序列更多数量的信号电平。 序列标识符基于数据序列是第一数据序列还是第二数据序列，在第一模式和第二模式之间改变多路复用器。 数据序列包括多个定时阶段。 序列检测器可以至少部分地基于数据序列的定时级来控制电路的环路带宽。

公开(公告)号：US08760789B2

公开(公告)日：2014-06-24

申请号：US13240745

申请日：2011-09-22

申请人： Marc Feller ,  Jaewook Lee ,  Umang Mehta

发明人： Marc Feller ,  Jaewook Lee ,  Umang Mehta

IPC分类号： G11B5/035

CPC分类号： G11B20/025 ,  G11B5/09 ,  G11B20/10046 ,  G11B20/10203 ,  G11B20/10231 ,  G11B20/10314 ,  G11B20/10324 ,  G11B20/1492 ,  G11B2220/2508

摘要： In one embodiment, a read channel comprises: a preprocessor for receiving a first signal and producing a second signal from the first signal using current values of a positive coefficient, a zero coefficient, and a negative coefficient; an interpolator for producing a third signal based on the second signal; and a slicer for producing a fourth signal from the third signal by estimating a level for the third signal. The fourth signal is at one of three levels consisting of a positive level, a zero level, and a negative level. For every n first signals received by the preprocessor, the current value of one of the positive coefficient, the zero coefficient, and the negative coefficient is adjusted depending on which of the three levels the fourth signal is at.

摘要翻译： 在一个实施例中，读通道包括：预处理器，用于接收第一信号，并使用正系数，零系数和负系数的当前值从第一信号产生第二信号; 用于基于所述第二信号产生第三信号的内插器; 以及切片器，用于通过估计第三信号的电平来从第三信号产生第四信号。 第四信号是由正电平，零电平和负电平组成的三个电平之一。 对于由预处理器接收的每n个第一信号，根据第四信号所处的三个电平中的哪一个来调整正系数，零系数和负系数之一的当前值。

公开(公告)号：US20130077187A1

公开(公告)日：2013-03-28

申请号：US13240745

申请日：2011-09-22

申请人： Marc Feller ,  Jaewook Lee ,  Umang Mehta

发明人： Marc Feller ,  Jaewook Lee ,  Umang Mehta

IPC分类号： G11B5/09

CPC分类号： G11B20/025 ,  G11B5/09 ,  G11B20/10046 ,  G11B20/10203 ,  G11B20/10231 ,  G11B20/10314 ,  G11B20/10324 ,  G11B20/1492 ,  G11B2220/2508

摘要： In one embodiment, a read channel comprises: a preprocessor for receiving a first signal and producing a second signal from the first signal using current values of a positive coefficient, a zero coefficient, and a negative coefficient; an interpolator for producing a third signal based on the second signal; and a slicer for producing a fourth signal from the third signal by estimating a level for the third signal. The fourth signal is at one of three levels consisting of a positive level, a zero level, and a negative level. For every n first signals received by the preprocessor, the current value of one of the positive coefficient, the zero coefficient, and the negative coefficient is adjusted depending on which of the three levels the fourth signal is at.

摘要翻译： 在一个实施例中，读通道包括：预处理器，用于接收第一信号，并使用正系数，零系数和负系数的当前值从第一信号产生第二信号; 用于基于所述第二信号产生第三信号的内插器; 以及切片器，用于通过估计第三信号的电平来从第三信号产生第四信号。 第四信号是由正电平，零电平和负电平组成的三个电平之一。 对于由预处理器接收的每n个第一信号，根据第四信号所处的三个电平中的哪一个来调整正系数，零系数和负系数之一的当前值。

公开(公告)号：US20080158025A1

公开(公告)日：2008-07-03

申请号：US11619364

申请日：2007-01-03

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B2220/2516

摘要： The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N≦2k−2+k−1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k−1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

摘要翻译： 所要求保护的实施例提供了针对数据的游程限制（RLL）编码的方法，装置和系统。 在一个实施方式中，对于任何速率N /（N + 1），其中N <= 2K-2 + k-1，构建游程长度不超过k的可级联的RLL码。 随着代码率的增加，k的值从最小可能值的角度比许多其他代码的值更慢。 此外，k位运行长度的出现仅在两个码字的接合处发生。 因此，代码主要是k-1。 这种质量使得代码非常适用于诸如LDPC通道的奇偶校验位插入应用。 在一个实施方式中，该方法将违反序列的位地址放置在码字开始处的表中，并且占据表条目所在位置的用户数据被移动到违规序列的位置。 这是迭代地进行的，并且以一种方式提供了违反序列在地址表本身内的情况。

公开(公告)号：US08433965B2

公开(公告)日：2013-04-30

申请号：US12880740

申请日：2010-09-13

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10231 ,  G11B20/10379 ,  G11B2220/20 ,  G11B2220/90 ,  H03M13/39 ,  H03M13/41

摘要： A digital data recovery system for converting a suboptimal signal into a converted signal that closely approximates an original signal includes a first data filter, a first interpolator and a second interpolator. The first data filter filters the suboptimal signal to generate a first filtered signal. The first interpolator receives the first filtered signal and generates a first interpolated signal. Substantially concurrently, the second interpolator receives the suboptimal signal and generates a second interpolated signal. The digital data recovery system may further comprise a second data filter that receives the second interpolated signal and generates a second filtered signal. Further, the first data filter can include a set of first coefficients and the second data filter can include a set of second coefficients. Moreover, the second coefficients can be updated and subsequently transformed in order to update the first coefficients.

摘要翻译： 用于将次最佳信号转换为接近原始信号的转换信号的数字数据恢复系统包括第一数据滤波器，第一内插器和第二内插器。 第一数据滤波器滤除次优信号以产生第一滤波信号。 第一内插器接收第一滤波信号并产生第一内插信号。 基本同时，第二内插器接收次优信号并产生第二内插信号。 数字数据恢复系统还可以包括接收第二内插信号并产生第二滤波信号的第二数据滤波器。 此外，第一数据滤波器可以包括一组第一系数，并且第二数据滤波器可以包括一组第二系数。 此外，可以更新第二系数并随后变换以更新第一系数。

公开(公告)号：US07961818B2

公开(公告)日：2011-06-14

申请号：US12024807

申请日：2008-02-01

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： H04L27/14

CPC分类号： G11B5/59616

摘要： Timing recovery in partial-response-based magnetic recording systems customarily employs the “decision-directed” method wherein phase error is recovered from the differences between the noise-corrupted received signal samples and their estimated ideal (noise and phase error free) values. The filtered phase error drives a numerically-controlled oscillator which determines the instants at which the signal is resampled, attempting to place said instants at the ideal sampling times. The resampled signal contains errors due to mistiming as well as to the original corrupting noise, and these errors directly influence the success of subsequent detection. However, the noise can be reduced using adaptive linear prediction, having the effect of reducing the output error for a given noise input, or maintaining the same error for a larger noise input.

摘要翻译： 基于部分响应的磁记录系统的定时恢复通常采用“判决导向”方法，其中相位误差是从噪声损坏的接收信号样本与其估计的理想（无噪声和无相位误差）值之间的差异中恢复的。 滤波的相位误差驱动数控振荡器，其确定信号被重新采样的时刻，试图将所述时刻放置在理想​​的采样时间。 重采样信号由于错误以及原始的破坏性噪声而包含误差，这些误差直接影响后续检测的成功。 然而，可以使用自适应线性预测来降低噪声，具有减小给定噪声输入的输出误差的效果，或者为更大的噪声输入保持相同的误差。

公开(公告)号：US07429937B2

公开(公告)日：2008-09-30

申请号：US11619364

申请日：2007-01-03

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B2220/2516

摘要： The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N≦2k−2+k−1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k−1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

摘要翻译： 所要求保护的实施例提供了针对数据的游程限制（RLL）编码的方法，装置和系统。 在一个实施方式中，对于任何速率N /（N + 1），其中N <= 2K-2 + k-1，构建游程长度不超过k的可级联的RLL码。 随着代码率的增加，k的值从最小可能值的角度比许多其他代码的值更慢。 此外，k位运行长度的出现仅在两个码字的接合处发生。 因此，代码主要是k-1。 这种质量使得代码非常适用于诸如LDPC通道的奇偶校验位插入应用。 在一个实施方式中，该方法将违反序列的位地址放置在码字开始处的表中，并且占据表条目所在位置的用户数据被移动到违规序列的位置。 这是迭代地进行的，并且以一种方式提供了违反序列在地址表本身内的情况。

公开(公告)号：US20090034646A1

公开(公告)日：2009-02-05

申请号：US11830570

申请日：2007-07-30

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： H04B15/00

CPC分类号： H03M13/3922 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10175 ,  G11B20/10203 ,  G11B20/10296 ,  G11B2220/2516 ,  H03M13/3972 ,  H03M13/6343

摘要： An estimator of the noiseless output of a noisy partial response channel is described. The estimator operates recursively. In each iteration, the estimator processes a window of the N most recently received noisy channel outputs to compare output level metrics for all possible channel output level, and selects a noiseless output level with maximal posterior probability.

摘要翻译： 描述了噪声部分响应信道的无噪声输出的估计器。 估计器递归运算。 在每次迭代中，估计器处理N个最近接收的噪声信道输出的窗口以比较所有可能的信道输出电平的输出电平度量，并且选择具有最大后验概率的无噪声输出电平。

公开(公告)号：US20080310522A1

公开(公告)日：2008-12-18

申请号：US11763009

申请日：2007-06-14

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： H04L27/28

CPC分类号： H03M13/39

摘要： An estimator of the noiseless output of a noisy partial response channel is described. The estimator operates recursively. In each iteration, the estimator processes a window of the N most recently received noisy channel outputs to compare subsequence metrics for all possible channel output subsequences of length N, and selects a noiseless subsequence with maximal posterior probability. One noiseless sample of the selected subsequence is output as an estimate of one of the channel outputs.

摘要翻译： 描述了噪声部分响应信道的无噪声输出的估计器。 估计器递归运算。 在每次迭代中，估计器处理N个最近接收的噪声信道输出的窗口，以比较长度为N的所有可能的信道输出子序列的子序列度量，并选择具有最大后验概率的无噪声子序列。 输出所选子序列的一个无噪声样本作为其中一个通道输出的估计。

公开(公告)号：US20060132950A1

公开(公告)日：2006-06-22

申请号：US11316609

申请日：2005-12-21

申请人： Marc Feller

发明人： Marc Feller

IPC分类号： G11B20/10 ,  G11B5/584

CPC分类号： G11B5/584 ,  G11B20/10009 ,  H03K5/1532

摘要： A method and device for detecting a peak which is substantially the same as the actual peak are disclosed. In one embodiment, the device includes a filter, a shift register, a controller and a digital interpolator. The filter is configured to receive a plurality of signal samples and the shift register, which is coupled with the filter, has multiple registers. The shift register is configured to receive the plurality of signal samples and to shift the plurality of signal samples through the registers. The controller is coupled with the shifter register and is configured to detect a zero-crossing event in the signal samples. The digital interpolator is coupled with the controller and configured to perform a binary search to identify a peak substantially the same as the actual peak.

摘要翻译： 公开了一种用于检测与实际峰值基本相同的峰值的方法和装置。 在一个实施例中，该装置包括滤波器，移位寄存器，控制器和数字内插器。 滤波器被配置为接收多个信号采样，并且与滤波器耦合的移位寄存器具有多个寄存器。 移位寄存器被配置为接收多个信号样本并且通过寄存器移位多个信号样本。 控制器与移位器寄存器耦合，并被配置为检测信号采样中的过零事件。 数字内插器与控制器耦合并被配置为执行二进制搜索以识别与实际峰值基本相同的峰值。