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公开(公告)号：US20140380018A1
公开(公告)日：2014-12-25
申请号：US13926564
申请日：2013-06-25
申请人： James E. Phillips , Wing Shek Wong , Charles Vitu
发明人： James E. Phillips , Wing Shek Wong , Charles Vitu
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F9/3001 , G06F9/32
摘要： In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括多个核。 每个核心包括用于接收包括非翻译存储器地址的指令的转换功率逻辑，确定代码段（CS）基地址是否等于零，并且响应于CS基地址等于零的确定，执行指令 使用非翻译的内存地址。 描述和要求保护其他实施例。
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公开(公告)号：US20160179552A1
公开(公告)日：2016-06-23
申请号：US14581101
申请日：2014-12-23
申请人： Wing Shek Wong , James E. Phillips
发明人： Wing Shek Wong , James E. Phillips
CPC分类号： G06F9/3838
摘要： A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.
摘要翻译： 处理器包括核心和调度器。 调度器包括第一和第二依赖矩阵和就绪确定单元。 调度器还包括排队第一父操作，第二父操作和子操作的逻辑，该操作包括取决于第一和第二父操作的第一和第二源。 调度器还包括分别在第一和第二依赖矩阵中存储子操作的第一和第二源的物理地址的逻辑。 此外，调度器包括分别执行第一和第二父操作的目的地的相应物理地址与子操作的第一和第二源的相应物理地址之间的标签比较的逻辑。 此外，准备确定单元包括基于标签比较来确定子操作准备好发送的逻辑。
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3.发明申请Execute at commit state update instructions, apparatus, methods, and systems 有权在提交状态更新指令，设备，方法和系统上执行公开(公告)号：US20120079488A1
公开(公告)日：2012-03-29
申请号：US12924311
申请日：2010-09-25
IPC分类号： G06F9/46
CPC分类号： G06F9/30087 , G06F9/3842 , G06F9/3857
摘要： An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.
摘要翻译： 一种包括执行逻辑的装置，包括执行指令的电路以及与执行逻辑耦合的指令执行调度器逻辑。 指令执行调度器逻辑是在提交状态更新指令下接收执行。 指令执行调度器逻辑包括提交状态更新逻辑，等待在提交状态更新指令执行执行，直到执行提交状态更新指令是下一个提交指令。 还公开了其他装置，方法和系统。
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公开(公告)号：USRE35311E
公开(公告)日：1996-08-06
申请号：US292606
申请日：1994-08-18
CPC分类号： G06F9/3853 , G06F7/575 , G06F9/3001 , B01F2003/0896 , G06F7/4991
摘要： A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.
摘要翻译： 用于数字数据处理的多功能ALU（算术/逻辑单元）有助于并行执行指令，从而提高处理器的性能。 所提出的装置减少了由流水线机器中的数据依赖性危害引起的指令执行延迟。 这种延迟减少是由于这些危害而使互锁崩溃而实现的。 所提出的装置实现性能改进，同时保持与使用相同架构设计的先前实现的兼容性。
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5.发明授权Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode 失效用于在循环或非循环模式下旋转和操纵输入数据字节的位的顺序的多功能置换开关
公开(公告)号：US5471628A
公开(公告)日：1995-11-28
申请号：US906729
申请日：1992-06-30
CPC分类号： G06F7/762 , G06F9/30018 , G06F9/30032
摘要： In a digital computer system both rotation of bits in a data byte and rotation in combination with additional manipulation, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the sequence of input bits are maintained on the output bit lines when the bits on the input lines are considered as arranged in a circle, and in a non-cyclic mode of operation, connects the input bit lines to the output bit lines in a manner to execute gather operations and spread operations.
摘要翻译： 在数字计算机系统中，循环运行模式中的数据字节中的位的旋转以及附加操作的多个功能置换开关的组合将输入位线连接到输出位线，使得输入位序列 被保持在输出位线上，当输入线上的位被认为是排列成一个圆时，并且在非循环操作模式中，以输入位线连接到输出位线以执行采集操作，并且 传播操作。
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公开(公告)号：US4635335A
公开(公告)日：1987-01-13
申请号：US831428
申请日：1986-02-20
申请人： Trevor J. Brown , James E. Phillips
发明人： Trevor J. Brown , James E. Phillips
CPC分类号： B60B7/08 , B23P19/047 , B25B27/02 , B60B7/10 , Y10T29/53657 , Y10T29/53687 , Y10T29/53709
摘要： Apparatus is disclosed for attaching a flexible annular member to a rigid member using an annular tongue on an annular bead on one of the members that is engageable in an annular groove in an annular bead on the other member, and further using a preformed resilient lock ring that is split so as to have oppositely facing ends and has a C-shaped cross-section with a radially outwardly facing peripheral side so as to be mountable over and then clamp together and hold the beads on the members with their tongue and groove engaged.
摘要翻译： 公开了一种用于将柔性环形构件附接到刚性构件的装置，其使用在一个构件上的环形胎圈上的环形舌片，该环形胎圈可接合在另一构件上的环形胎圈中的环形槽中，并且还使用预成型的弹性锁定环 其分开以具有相对的端部并且具有带有径向向外的周向侧的C形横截面，以便可安装在其上，然后夹紧在一起，并且将其保持在构件上，并使其舌和槽接合。
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公开(公告)号：US5590348A
公开(公告)日：1996-12-31
申请号：US920962
申请日：1992-07-28
CPC分类号： G06F7/764 , G06F9/30032 , G06F9/30094 , G06F9/30167 , G06F9/3885
摘要： Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple functional units from which the appropriate status must be selected for controlling the sequencing of microinstructions. This is especially true in horizontally microcoded machines. The adverse affects on the delay can be reduced by using a staged multiplexor design. For the staged multiplexor to be useful, all functional unit status should be produced as early as possible. In this invention, a status predictor is described that allows the status associated with the shifter to be generated directly from the inputs to the shifter. As a result, the status is available early in the pipeline cycle in which the shift is actually performed and made available to the multiplexor producing the controls for microinstruction sequencing. In addition, the invention allows the early generation of all shifter status used to set condition codes. The predictor has been implemented in an ESA/390 processor implementation where it was instrumental in achieving the desired cycle time.
摘要翻译： 功能状态的产生，随后使用状态来控制微指令的排序是处理器设计中众所周知的关键路径。 与超标量机相关的延迟通过由多个功能单元产生的附加状态而加剧，由此必须选择适当的状态来控制微指令的排序。 在水平微编机器中尤其如此。 可以通过使用分段多路复用器设计来减少对延迟的不利影响。 为了使分级多路复用器有用，所有功能单元的状态应尽可能早地生成。 在本发明中，描述了状态预测器，其允许直接从移位器的输入产生与移位器相关联的状态。 因此，该状态在流水线周期的早期可用，其中实际执行移位并使其可用于产生用于微指令排序的控制的多路复用器。 此外，本发明允许早期生成用于设置条件代码的所有移位器状态。 预测器已经在ESA / 390处理器实现中实现，它在实现期望的周期时间方面发挥了重要作用。
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公开(公告)号：US5576765A
公开(公告)日：1996-11-19
申请号：US214929
申请日：1994-03-17
申请人： Dennis P. Cheney , Vincent C. Conzola , Chuck H. Ngai , Richard T. Pfeiffer , James E. Phillips
发明人： Dennis P. Cheney , Vincent C. Conzola , Chuck H. Ngai , Richard T. Pfeiffer , James E. Phillips
CPC分类号： H04N19/00 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/70
摘要： A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.
摘要翻译： 一种用于接收压缩编码数字化视频信号并发送解压缩解码数字视频信号的数字信号解码器系统包括FIFO数据缓冲器，具有（1）压缩编码数据缓冲器的RAM，以及（2）用于存储解压缩数字视频缓冲器 数据。 提供了用于管理RAM的存储器管理单元。 解码器具有解码器处理器，其包括用于接收编码数据的可变长度码解码器，用于对解码数据进行去量化的（2,3,3）并行计数器逆量化器，用于变换去量化的解码数据的逆离散余弦变换解码器 内插图像，预测图像和双向预测图像，用于从RAM接收图像内容和其他信息的运动补偿器和误差函数，以及形成用于返回到RAM的运动补偿预测图像;显示单元，用于从 RAM和精简指令集控制器来控制存储器管理单元，可变长度码解码器，逆量化器，逆离散余弦变换解码器，运动补偿器和显示单元。
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9.发明授权Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions 失效在可复合指令集机器中的三操作数异常的溢出确定，其复合两个算术指令
公开(公告)号：US5301341A
公开(公告)日：1994-04-05
申请号：US619868
申请日：1990-11-28
CPC分类号： G06F7/575 , G06F9/3001 , G06F9/3836 , G06F9/3857 , G06F7/4991
摘要： A mechanism is presented for detecting overflow in an interlock collapsing hardware apparatus that simultaneously executes two instructions. The overflow is determined as if the second instruction executes by itself using results from execution of the first instruction. Overflow detection is accomplished by using only values input into, and generated within, the interlock collapsing apparatus.
摘要翻译： 提出一种机构，用于检测同时执行两个指令的互锁堆叠硬件设备中的溢出。 确定溢出就好像第二条指令本身使用执行第一条指令的结果一样执行。 溢出检测是通过仅使用输入到互锁收缩装置中并在其内产生的值来实现的。
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公开(公告)号：US08966230B2
公开(公告)日：2015-02-24
申请号：US12571379
申请日：2009-09-30
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3873
摘要： Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.
摘要翻译： 描述与执行阶段的动态选择有关的方法和装置。 在一些实施例中，逻辑可以确定是否在处理器中的多个级中的一个处执行指令。 在一些实施例中，多个阶段至少对应于该指令的地址生成阶段或执行阶段。 还描述和要求保护其他实施例。
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