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    Method of forming a field effect transistor
    1.
    发明授权
    Method of forming a field effect transistor 失效
    形成场效应晶体管的方法

    公开(公告)号：US06599789B1

    公开(公告)日：2003-07-29

    申请号：US09713844

    申请日：2000-11-15

    申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    IPC分类号： H01L2184

    CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

    摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

    摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。 源极/漏极区域形成在沟道区域的相对侧上。 绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。 形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。 半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。 半导体通道材料形成在空隙内。 相邻的源极/漏极区域横向靠近通道材料提供。 在通道材料上形成一个栅极。 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。

    Method of forming a field effect transistor with halo implant regions
    3.
    发明授权
    Method of forming a field effect transistor with halo implant regions 有权
    用卤素注入区域形成场效应晶体管的方法

    公开(公告)号：US07153731B2

    公开(公告)日：2006-12-26

    申请号：US10236662

    申请日：2002-09-05

    申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

    摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

    摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。 源极/漏极区域形成在沟道区域的相对侧上。 绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。 形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。 半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。 半导体通道材料形成在空隙内。 相邻的源极/漏极区域横向靠近通道材料提供。 在通道材料上形成一个栅极。 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。

    Method of forming a field effect transistor
    4.
    发明授权
    Method of forming a field effect transistor 有权

    公开(公告)号：US07112482B2

    公开(公告)日：2006-09-26

    申请号：US10901538

    申请日：2004-07-28

    申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

    摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

    Integrated transistor circuitry
    5.
    发明授权
    Integrated transistor circuitry 失效
    集成晶体管电路

    公开(公告)号：US06987291B2

    公开(公告)日：2006-01-17

    申请号：US10236282

    申请日：2002-09-05

    申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    IPC分类号： H01L31/0328

    CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

    摘要： Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

    摘要翻译： 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。

    Sidewall strap for complementary semiconductor structures and method of making same
    7.
    发明授权
    Sidewall strap for complementary semiconductor structures and method of making same 失效
    互补半导体结构的侧壁带及其制造方法

    公开(公告)号：US06806134B2

    公开(公告)日：2004-10-19

    申请号：US10205131

    申请日：2002-07-24

    申请人： Jigish D. Trivedi ,  Todd R. Abbott ,  Zhongze Wang

    发明人： Jigish D. Trivedi ,  Todd R. Abbott ,  Zhongze Wang

    IPC分类号： H01L218238

    CPC分类号： H01L21/823842 ,  H01L21/823864 ,  H01L21/823871

    摘要： Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two sides, and two ends; and a conductive inhibitor strip that adjoins a portion of one of the two sides of the p-type strip and a portion of one of the two sides of the n-type strip so as to inhibit cross-diffusion between the p-type strip and the n-type strip while electrical connection between n-type and p-type polycrystalline silicon is maintained.

    摘要翻译： 讨论了使用双掺杂多晶硅增强器件的器件，结构和方法。 本发明的一个方面包括具有顶部，底部，两侧和两端的p型条带; 具有顶部，底部，两侧和两端的n型条带; 以及导电抑制带，其邻接p型条的两侧中的一方的一部分和n型条的两侧的一部分中的一部分，以便抑制p型条和 同时保持n型和p型多晶硅之间的电连接。

    Methods of forming conductive contacts
    9.
    发明授权
    Methods of forming conductive contacts 有权

    公开(公告)号：US06673715B2

    公开(公告)日：2004-01-06

    申请号：US10002335

    申请日：2001-10-24

    申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Chi-Chen Cho

    发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Chi-Chen Cho

    IPC分类号： H01L2144

    CPC分类号： H01L21/76888 ,  H01L21/76897

    摘要： Methods of forming conductive contacts are described. According to one implementation, the method includes forming a transistor gate structure over a substrate. The gate structure includes a conductive silicide covered by insulative material. A dielectric layer is formed over the substrate and the gate structure. A contact opening is etched into the dielectric layer adjacent the gate structure. After the etching, the substrate is exposed to oxidizing conditions effective to oxidize any conductive silicide within the contact opening which was exposed during the contact opening etch. After the oxidizing, conductive material is formed within the contact opening. According to another embodiment, after the etching, it is determined whether conductive silicide of the gate structure was exposed during the etching. The substrate is then exposed to oxidizing conditions only if conductive silicide of the gate structure was exposed during the etching.