公开(公告)号：US08358555B2

公开(公告)日：2013-01-22

申请号：US12835978

申请日：2010-07-14

Applicant: Jin Youp Cha ,  Jae Jin Lee

Inventor： Jin Youp Cha ,  Jae Jin Lee

IPC: G11C17/18 ,  G11C17/00 ,  H01H85/00

CPC classification number: G11C17/16 ,  G11C29/785

Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.

Abstract translation: 熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。

公开(公告)号：US08867287B2

公开(公告)日：2014-10-21

申请号：US13586047

申请日：2012-08-15

Applicant: Jin Youp Cha ,  Jae Il Kim

Inventor： Jin Youp Cha ,  Jae Il Kim

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/40 ,  G11C29/12 ,  G11C29/14

CPC classification number: G11C29/40 ,  G11C29/34 ,  G11C2029/2602

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract translation: 一种半导体存储装置，包括测试电路，该测试电路被配置为通过在第一测试模式期间比较和压缩存储在存储体内的多个存储单元中的数据来产生压缩数据，并且被配置为将压缩数据作为测试数据输出到输入/输出 在第一测试模式期间通过一个所选择的全局线填充测试电路，并且测试电路被配置为在第二测试模式期间将压缩数据发送到多个全局线路，在第二测试模式期间组合加载在各个全局线路中的压缩数据 并且在第二测试模式期间将组合结果作为测试数据输出到输入/输出焊盘。

公开(公告)号：US08749298B2

公开(公告)日：2014-06-10

申请号：US13585972

申请日：2012-08-15

Applicant: Jin Youp Cha ,  Jae Il Kim

Inventor： Jin Youp Cha ,  Jae Il Kim

IPC: H01H37/76 ,  H01H85/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.

Abstract translation: 反熔丝电路包括：反熔丝单元，其包括能够响应于破裂信号被编程的反熔丝，并且被配置为产生对应于反熔丝的状态的熔丝信号; 虚拟熔丝单元，其包括虚拟熔丝并且被配置为产生对应于所述虚拟熔丝的状态的虚拟熔丝信号; 以及阻挡单元，被配置为响应于所述虚拟熔丝信号的状态而将所述熔丝信号输出为熔丝输出信号。

公开(公告)号：US08717087B2

公开(公告)日：2014-05-06

申请号：US13589205

申请日：2012-08-20

Applicant: Jin Youp Cha ,  Jae Il Kim

Inventor： Jin Youp Cha ,  Jae Il Kim

IPC: H01H37/76

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode.

Abstract translation: 反熔丝电路包括：破裂单元，包括在编程模式期间响应于输入断裂信号编程的反熔丝，并且被配置为产生对应于反熔丝的状态的输出断裂信号以输出所产生的输出 电压钳位单元，被配置为产生与外部电压电平成比例的钳位电压，以在外部电压电平上升到预定电平以上时生成具有恒定电压电平的钳位电压;以及熔丝信号 生成单元，被配置为在编程模式的初始阶段将传输节点复位为钳位电压，以在输出模式期间响应于传输节点的电压电平生成熔丝信号。

公开(公告)号：US09013950B2

公开(公告)日：2015-04-21

申请号：US13586155

申请日：2012-08-15

Applicant: Jin Youp Cha ,  Jae Il Kim

Inventor： Jin Youp Cha ,  Jae Il Kim

IPC: G11C8/00 ,  G11C8/18 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10

CPC classification number: G11C7/12 ,  G11C8/10

Abstract: A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal.

Abstract translation: 列选择信号生成电路包括：第一电流控制器，被配置为响应于存储体活动信号来控制预列选择信号的电平，驱动器被配置为响应于预列选择产生放大列选择信号 信号和第二电流控制器，其被配置为响应于存储体有效信号而产生驱动器的输出信号作为列选择信号。