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1.发明授权Modulation of a digital input signal using a digital signal modulator and signal splitting 有权使用数字信号调制器和信号分离调制数字输入信号公开(公告)号：US06693571B2
公开(公告)日：2004-02-17
申请号：US10325145
申请日：2002-12-20
IPC分类号： H03M300
CPC分类号： H02M3/1584 , H02M3/157 , H03F3/2173 , H03F2200/331 , H03K7/08
摘要： A digital signal modulator modulates a digital input signal to drive a load, such as an opposed current amplifier or other opposed current converter. The combinations of frequency relationships and digital signal modulator elements provide significant digital signal processing capabilities and flexible output signal timing. In one embodiment, a digital signal modulator modulates a digital input signal. Even and odd samples of the input signal propagate along two respective channels (signal paths), which include further digital processing capabilities, such as pulse width modulation, to generate output signals appropriate for the topology of a load. Additionally, a bias signal may be modulated with the digital input signal. By utilizing digital signal processing to modulate the input signal, various processing technologies are applied to the input signal. For example, noise shaping may be implemented using a delta-sigma modulator as an input stage to the two channels.
摘要翻译： 数字信号调制器调制数字输入信号以驱动负载，例如相对的电流放大器或其它相对的电流转换器。 频率关系和数字信号调制器元件的组合提供了显着的数字信号处理能力和灵活的输出信号时序。 在一个实施例中，数字信号调制器调制数字输入信号。 输入信号的偶数和奇数样本沿着两个相应的通道（信号路径）传播，其包括进一步的数字处理能力，例如脉冲宽度调制，以产生适合负载拓扑的输出信号。 另外，可以用数字输入信号调制偏置信号。 通过利用数字信号处理来调制输入信号，各种处理技术被应用于输入信号。 例如，可以使用Δ-Σ调制器作为两个通道的输入级来实现噪声整形。
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2.发明授权Modulation of a digital input signal using multiple digital signal modulators 有权使用多个数字信号调制器调制数字输入信号公开(公告)号：US06762704B1
公开(公告)日：2004-07-13
申请号：US10314804
申请日：2002-12-09
申请人： John L. Melanson , Jack B. Andersen
发明人： John L. Melanson , Jack B. Andersen
IPC分类号： H03M300
摘要： A digital input signal is modulated using multiple digital signal modulators operating at a variety of clock frequencies and clock frequency phase relationships to drive a load, such as an opposed current amplifier or other opposed current converter. The combinations of frequency relationships and digital signal modulator elements provide significant digital signal processing capabilities and flexible output signal timing. In one embodiment, a digital input signal, which may be biased, is modulated by multiple digital signal modulators to generate corresponding output signals. The corresponding output signals are utilized to drive a load, such as a half bridge, opposed current amplifier and to produce a single output signal. By adjusting the phase relationships between the clock frequencies, various output signal characteristics are achieved. Additionally, by utilizing digital signal processing to modulate the input signal, various processing technologies are applied to the input signal. For example, noise shaping may be implemented using delta-sigma modulators as one stage in digital signal modulators.
摘要翻译： 使用在各种时钟频率和时钟频率相位关系下操作的多个数字信号调制器来调制数字输入信号，以驱动诸如相对的电流放大器或其它相对的电流转换器之类的负载。 频率关系和数字信号调制器元件的组合提供了显着的数字信号处理能力和灵活的输出信号时序。 在一个实施例中，可以被偏置的数字输入信号由多个数字信号调制器调制以产生相应的输出信号。 相应的输出信号用于驱动负载，例如半桥，相对电流放大器，并产生单个输出信号。 通过调整时钟频率之间的相位关系，实现各种输出信号特性。 此外，通过利用数字信号处理来调制输入信号，各种处理技术被应用于输入信号。 例如，可以使用delta-sigma调制器作为数字信号调制器中的一个阶段来实现噪声整形。
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公开(公告)号：US07970088B2
公开(公告)日：2011-06-28
申请号：US12343317
申请日：2008-12-23
IPC分类号： H04L7/00
CPC分类号： H03F3/217 , H03F2200/03 , H03H17/0275 , H03H17/0642 , H03H17/0685
摘要： Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.
摘要翻译： 提供了用于将具有可变输入采样率的输入数据流转换为输出采样率的系统和方法，哪些系统和方法用于处理数据流。 在一个实施例中，系统包括时钟源，被配置为对相应数据流计数周期的计数器和数据处理器。 数据处理器被配置为读取由接收到的帧同步信号之间的计数器计数的周期数，并且基于相应的计数周期将第一数据流转换成预定的输出采样率。
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4.发明授权Streaming multi-channel audio as packetized data or parallel data with a separate input frame sync 失效将多通道音频流作为分组数据或具有单独输入帧同步的并行数据公开(公告)号：US07738613B1
公开(公告)日：2010-06-15
申请号：US10805574
申请日：2004-03-20
IPC分类号： H04L7/00
CPC分类号： H04L7/0029 , H03H17/0275 , H03H17/0685 , H04L7/005 , H04L25/4902
摘要： Systems and methods for converting a data stream from a first sample rate to a second sample rate, where the data is received in bursts. In one embodiment, a method includes receiving bursty audio data on a first input line and receiving synchronization data on a second input line that is separate from the first input line. An input sample rate is then estimated for the received audio data based on the received synchronization data and the audio data is converted to an output sample rate. The input sample rate is determined by counting samples received in a time interval and potentially low-pass filtering the result. The audio data may be in packetized, parallel, or other forms, and the synchronization data may include individual signals, such as pulses or bits received at regular or irregular intervals.
摘要翻译： 用于将数据流从第一采样率转换为第二采样率的系统和方法，其中数据以突发方式接收。 在一个实施例中，一种方法包括在第一输入线上接收突发音频数据，并在与第一输入线分开的第二输入线上接收同步数据。 然后，基于接收到的同步数据对接收到的音频数据估计输入采样率，并将音频数据转换为输出采样率。 输入采样率通过对在时间间隔中接收到的样本进行计数并潜在地对结果进行低通滤波来确定。 音频数据可以是打包的，并行的或其他形式，并且同步数据可以包括各种信号，例如以规则或不规则的间隔接收的脉冲或位。
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公开(公告)号：US07576606B2
公开(公告)日：2009-08-18
申请号：US11782708
申请日：2007-07-25
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译： 使用低延迟校正器的数字开关放大器性能改进的系统和方法。 在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。 放大器还包括低延迟校正器，其被配置为接收由工厂输出的信号。 低延迟校正器的输出作为反馈被添加到输入音频信号。 该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。 可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。 可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。
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公开(公告)号：US20090143884A1
公开(公告)日：2009-06-04
申请号：US12343317
申请日：2008-12-23
CPC分类号： H03F3/217 , H03F2200/03 , H03H17/0275 , H03H17/0642 , H03H17/0685
摘要： Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.
摘要翻译： 提供了用于将具有可变输入采样率的输入数据流转换为输出采样率的系统和方法，哪些系统和方法用于处理数据流。 在一个实施例中，系统包括时钟源，被配置为对相应数据流计数周期的计数器和数据处理器。 数据处理器被配置为读取由接收到的帧同步信号之间的计数器计数的周期数，并且基于相应的计数周期将第一数据流转换成预定的输出采样率。
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公开(公告)号：US20090027117A1
公开(公告)日：2009-01-29
申请号：US11782702
申请日：2007-07-25
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38
CPC分类号： H03F1/3258 , H03F1/26 , H03F1/3241 , H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译： 使用低通滤波技术降低噪声和失真的数字开关放大器性能改进的系统和方法。 在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。 放大器还包括一个低通滤波器，用于滤除工厂输出的音频信号。 工厂的滤波输出作为反馈被添加到输入音频信号。 该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。 可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。 可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。
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8.发明申请公开(公告)号：US20070194845A1
公开(公告)日：2007-08-23
申请号：US11672321
申请日：2007-02-07
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： Systems and methods for minimizing errors due to component variation in switching amplifiers utilizing power supply feed forward techniques. One embodiment comprises a digital PWM amplifier having an amplification subsystem for receiving a digital audio signal and producing an analog output signal. The amplifier includes a power supply feed-forward path configured to modify the digital audio signal based on a power supply measurement. The feed-forward path includes an analog filter configured to filter the power supply measurement, as well as correction circuitry configured to correct component mismatch errors introduced by the filter. The power supply measurement may be a power supply difference, a power supply common mode, or both. In either case, the power supply measurement is corrected by multiplying the measurement by an appropriately scaled power supply difference.
摘要翻译： 利用电源前馈技术最小化开关放大器中元件变化的误差的系统和方法。 一个实施例包括具有用于接收数字音频信号并产生模拟输出信号的放大子系统的数字PWM放大器。 放大器包括配置为基于电源测量修改数字音频信号的电源前馈路径。 前馈路径包括被配置为滤波电源测量的模拟滤波器以及被配置为校正由滤波器引入的组件失配错误的校正电路。 电源测量可以是电源差异，电源共模或两者。 在任一情况下，通过将测量乘以适当缩放的电源差异来校正电源测量。
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9.发明申请Systems and Methods for Improving Performance in a Digital Amplifier by Adding an Ultrasonic Signal to an Input Audio Signal 失效通过向输入音频信号添加超声波信号来提高数字放大器性能的系统和方法公开(公告)号：US20070170984A1
公开(公告)日：2007-07-26
申请号：US11626569
申请日：2007-01-24
申请人： Jack B. Andersen , Peter G. Craven
发明人： Jack B. Andersen , Peter G. Craven
IPC分类号： H03F3/38
CPC分类号： H03F3/217 , H03F1/3264 , H03F3/2173 , H03F2200/03 , H03F2200/114 , H03F2200/351 , H03F2201/3236 , H03K17/162 , H03K17/6871
摘要： Systems and methods in which an ultrasonic signal is introduced into an audio signal before the audio signal is amplified by a switching amplifier. The added ultrasonic signal (e.g., a tone at half the amplifier's switching frequency) shifts the signals input to a set of power switches so that they do not switch nearly simultaneously. The ultrasonic signal causes the output current to be well defined to eliminate dead time distortion at low signal levels. Adding the tone ultrasonic signal causes the distortion to shift to an amplitude greater than zero. Signals that exceed this amplitude will experience the distortion, but the distortion will be less noticeable than in lower-amplitude signals. Signals that do not exceed this amplitude will not experience the distortion at all. Adding an ultrasonic signal may also draw energy away from the switch frequency and its harmonics to interference with AM radio reception.
摘要翻译： 在音频信号被开关放大器放大之前，将超声波信号引入到音频信号中的系统和方法。 增加的超声波信号（例如，放大器开关频率的一半处的音调）将输入的信号移动到一组电源开关，使得它们几乎不同时切换。 超声波信号使得输出电流被良好地定义，以消除低信号电平下的死区失真。 增加音调超声信号会导致失真转移到大于零的幅度。 超过该幅度的信号将经历失真，但是失真比在较低幅度信号中更不明显。 不超过此幅度的信号根本不会出现失真。 添加超声波信号也可能会从开关频率及其谐波中吸收能量，从而干扰AM无线电接收。
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公开(公告)号：USRE44525E1
公开(公告)日：2013-10-08
申请号：US13207232
申请日：2011-08-10
IPC分类号： H03F3/38
CPC分类号： H03F1/52 , H03F3/2173
摘要： Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.
摘要翻译： 使用低成本电流检测机制的全数字放大器中的过电流保护系统和方法。 过流硬切割单元接收数字音频信号，根据剪辑电平剪辑信号，并将信号提供给调制器。 调制器调制信号以产生例如PWM信号，并将调制信号提供给产生输出电流以驱动扬声器的输出级。 过流感测单元将输出电流与阈值进行比较，并产生指示输出电流是否超过阈值的二进制信号。 在二进制信号指示输出电流超过阈值的时间段期间，硬削波单元接收二进制信号并向下斜降电平。 当二进制信号指示输出电流不超过阈值时，硬限幅单元上升剪辑电平。
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