公开(公告)号：US4757441A

公开(公告)日：1988-07-12

申请号：US68769

申请日：1987-06-29

Applicant: Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

Inventor： Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

IPC: G06F3/153 ,  G09G5/22 ,  G06F13/10 ,  G06F15/16

CPC classification number: G09G5/222 ,  G06F3/153 ,  G09G2360/04

Abstract: A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices. The logic enables normal writes and reads to the video buffer to be suppressed or relocated to the virtual buffer, depending on the mode established by the main processor. A circular queue is established in memory to enable the main processor to selectively individually update the video buffer with the changes that have been made to the virtual buffer.

Abstract translation: 一种用于控制数据处理系统中的数据显示的方法和系统，所述数据处理系统包括主处理器，存储器子系统和输入/输出子系统，所述子系统包括用于在I / O总线上管理业务的I / O通道控制器，所述I / O通道控制器具有 附加协处理器和多个I / O设备，包括具有不同保留I / O地址空间的显示设备。 主处理器可以为具有不同保留的I / O地址空间的显示器建立不同的显示模式，这通常表示不同的显示类型。 在一种模式中，显示器专门分配给主处理器，并且协同处理器对该显示器的数据传输进行了尝试。 显示控制装置基于与协处理器相关联的逻辑电路，用于捕获具有在为显示设备保留的范围内的地址的指令。 根据主处理器建立的模式，该逻辑使得能够将视频缓冲区的正常写入和读取抑制或重新定位到虚拟缓冲区。 在存储器中建立循环队列以使得主处理器能够随着对虚拟缓冲器的改变而选择性地单独地更新视频缓冲器。

公开(公告)号：US4703420A

公开(公告)日：1987-10-27

申请号：US706804

申请日：1985-02-28

Applicant: John W. Irwin

Inventor： John W. Irwin

IPC: G06F13/362 ,  G06F13/20 ,  G06F13/36 ,  G06F13/18

CPC classification number: G06F13/20 ,  G06F13/36

Abstract: A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator. However, control is returned automatically to the co-processor in the absence of any other request, since the co-processor continually raises its access request line.

Abstract translation: 一种数据处理系统，具有通过输入/输出通道控制器选择性地连接到所述存储器子系统的主处理单元，存储器子系统和协处理器，所述控制装置包括用于仲裁所述协同处理器中的所述I / O总线的访问的控制装置， 处理器和连接到总线的其他I / O设备。 由于协处理器运行存储在存储器子系统中的程序，因此协处理器可以通过指令获取周期来垄断总线，从而将其他I / O设备排除在访问总线之前。 用于仲裁的控制装置基于协处理器具有最低优先级的线性优先级方案来响应请求。 除了协处理器之外，每个设备都允许控制总线，直到它自动放弃。 另一方面，协处理器响应于任何更高运营商的访问请求放弃总线的控制。 然而，由于协处理器不断提高其访问请求行，所以在没有任何其他请求的情况下，自动返回到协处理器的控制。

公开(公告)号：US4000779A

公开(公告)日：1977-01-04

申请号：US635859

申请日：1975-11-28

Applicant: John W. Irwin

Inventor： John W. Irwin

IPC: B01D45/06 ,  F24F13/22 ,  F25D21/14

CPC classification number: F24F13/22 ,  B01D45/06 ,  F24F1/0059 ,  Y10S165/197

Abstract: The present invention provides a condensate guide arranged in the path of a flow of air through an A-coil heat exchanger including slabs oriented generally horizontally relative to the air flow. The condensate guide is positioned downstream of the heat exchanger so that condensate when blown from the surface of the heat exchanger by the air flow therethrough impinges on the guide thereby removing it from the path of air and directing it to an appropriate drain.

Abstract translation: 本发明提供了一种冷凝液引导件，其布置在通过包括相对于空气流大致水平定向的板坯的A型线圈换热器的空气流的路径中。 冷凝引导件位于热交换器的下游，使得当通过空气流从热交换器的表面吹出时，冷凝物撞击在引导件上，从而将其从空气路径移除并将其引导到适当的排水管。

公开(公告)号：US4859815A

公开(公告)日：1989-08-22

申请号：US285921

申请日：1988-12-19

Applicant: John W. Irwin ,  James D. Wagoner

Inventor： John W. Irwin ,  James D. Wagoner

IPC: H04L29/10 ,  H04L1/00 ,  H04L25/49

CPC classification number: H04L25/4906 ,  H04L1/0083

Abstract: In a serial link in which it is necessary to occupy the link before and after transmission of a frame by sending a succession idle characters having alternating disparity effects, the disparity effect of the last character in the frame is compared with the disparity effect that would be produced by a disparity flip-flop, which has continued to step during frame transmission. If the disparity effect of these two characters match, no corrective action is required in order to resume the stream of idle characters. If the disparity effect of these characters differ, the disparity flip-flop is corrected before the stream of idle characters is resumed. Disclosed is hardware logic to accomplish this disparity control following transmission of frames in a transparent mode.

公开(公告)号：US4469026A

公开(公告)日：1984-09-04

申请号：US330866

申请日：1981-12-15

Applicant: John W. Irwin

Inventor： John W. Irwin

IPC: B41F23/04 ,  B41J11/00 ,  B41J3/04 ,  B41J5/44 ,  B41J13/08

CPC classification number: B41J11/0015 ,  B41F23/0443 ,  B41J11/002

Abstract: Printer having a sheet feed and drum transport assembly, an exit assembly and at least one dryer. Various print parameters or conditions are monitored relating to the drying of the ink on print media. These print parameters include print data density, ink characteristics and ambient humidity. The monitored print parameters are used to control the drying. In addition the monitored print parameters are used to control the detaching of the print media from a rotary transport. In this manner, the printer approaches an optimization of the drying and detaching function with respect to time and energy.

Abstract translation: 具有片材进给和鼓输送组件，出口组件和至少一个干燥器的打印机。 监控与打印介质上墨水干燥有关的各种打印参数或条件。 这些打印参数包括打印数据密度，墨水特性和环境湿度。 监控的打印参数用于控制干燥。 此外，监视的打印参数用于控制打印介质从旋转传送器的分离。 以这种方式，打印机接近关于时间和能量的干燥和分离功能的优化。

公开(公告)号：US4833596A

公开(公告)日：1989-05-23

申请号：US172042

申请日：1988-03-23

Applicant: Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

Inventor： Patrick A. Buckland ,  John W. Irwin ,  Jack E. Reeder

IPC: G06F3/153 ,  G09G5/22

CPC classification number: G06F3/153 ,  G09G5/222 ,  G09G2360/04

Abstract: A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. In a second mode, a display is time-shared between processors by establishing a virtual video buffer in main memory which is written into by one processor when the other processor has control of the display device. The contents of the virtual and real buffer are swapped whenever the display is reassigned to the other processor. In the third mode, co-processor data in the virtual buffer can be "windowed" onto the display device when it is assigned to the main processor. In the fourth mode, a display assigned to the co-processor displays data being run by code that is written to the displayed on a display device with a different pel resolution. The main processor does a pel conversion operation on the data in the process of transferring the data from the virtual buffer to the real buffer.

Abstract translation: 一种用于控制数据处理系统中的数据显示的方法和系统，所述数据处理系统包括主处理器，存储器子系统和输入/输出子系统，所述子系统包括用于在I / O总线上管理业务的I / O通道控制器，所述I / O通道控制器具有 附加协处理器和多个I / O设备，包括具有不同保留I / O地址空间的显示设备。 主处理器可以为具有不同保留的I / O地址空间的显示器建立不同的显示模式，这通常表示不同的显示类型。 在一种模式中，显示器专门分配给主处理器，并且协同处理器对该显示器的数据传输进行了尝试。 在第二模式中，通过在主存储器中建立虚拟视频缓冲器，在另一个处理器对显示设备进行控制时，由一个处理器写入显示器，在处理器之间进行时间共享。 每当将显示器重新分配给另一个处理器时，虚拟和实际缓冲区的内容将被交换。 在第三模式中，虚拟缓冲器中的协处理器数据在分配给主处理器时可以被“窗口化”到显示设备上。 在第四模式中，分配给协处理器的显示器以不同的像素分辨率显示正被写入显示设备上的代码运行的数据。 在将数据从虚拟缓冲器传送到实际缓冲器的过程中，主处理器对数据执行像素转换操作。

公开(公告)号：US4695945A

公开(公告)日：1987-09-22

申请号：US706802

申请日：1985-02-28

Applicant: John W. Irwin

Inventor： John W. Irwin

IPC: G06K9/00 ,  G06F13/24 ,  G06F13/26 ,  G06F13/28 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177

CPC classification number: G06F13/26 ,  G06F13/24 ,  G06F13/387 ,  G06F15/161

Abstract: A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

Abstract translation: 协处理器可连接到主系统数据总线，以运行主处理器未知的软件。 主处理器可以同时运行其他软件并通过提供并入随机存取存储器中的捕获逻辑并且由主处理器动态地加载来保持对共享I / O设施的优先级，该主处理器包含与共享处理器当前可用性有关的数据 I / O设备。 附加逻辑与协处理器相关联，用于管理协处理器和系统总线之间的中断。

公开(公告)号：US4187691A

公开(公告)日：1980-02-12

申请号：US933332

申请日：1978-08-14

Applicant: John W. Irwin

Inventor： John W. Irwin

IPC: F24F11/08 ,  F25B13/00 ,  F25B41/04

CPC classification number: F24F11/085 ,  F25B13/00 ,  F25B41/04

Abstract: The present invention relates to a split system air conditioner and more particularly to the indoor section which is provided with a refrigerant flow valve bypass arrangement that permits multiple orientation of the indoor section.

Abstract translation: 分体系统空调技术领域本发明涉及一种分体系统空调装置，更具体地说，涉及一种设有允许室内部分的多个定向的制冷剂流量旁通装置的室内部。

公开(公告)号：US4031521A

公开(公告)日：1977-06-21

申请号：US189576

申请日：1971-10-15

Applicant: Phil H. Hall ,  John W. Irwin

Inventor： Phil H. Hall ,  John W. Irwin

IPC: G06F9/22 ,  G06F9/16

CPC classification number: G06F9/226

Abstract: The disclosure teaches that a cyclable program loop can be alternatively used to selectively initiate subprograms or as a timing signal generator, the latter preferably in a maintenance mode of a machine in which the loop resides. A programmable machine has a cyclable program loop with a preset number of program steps. First sequences of internal machine operations cooperate with said loop such that, based upon detection of predetermined status signals, one of a plurality of object programs may be initiated. In a second mode of operation, the status signals are suppressed; and the cyclable program loop is selectively used in a second mode or as in said first mode. In a preferred form, the second mode, the cyclable program loop, is a timing cycle usable in connection with maintenance procedures on the programmable machine. At the expiration of each timing cycle, the loop supplies a reference signal for operating a second set of internal machine functions. Such timing operations are preferably interleaved with first mode functions.

Abstract translation: 该公开内容教导了可循环的程序循环可以替代地用于选择性地启动子程序或作为定时信号发生器，后者优选地处于循环驻留的机器的维护模式。 可编程机器具有可循环的程序循环，具有预设的程序步数。 内部机器操作的第一序列与所述环路协作，使得基于预定状态信号的检测，可以启动多个对象程序之一。 在第二操作模式中，抑制状态信号; 并且可循环程序循环在第二模式或所述第一模式中选择性地使用。 在优选形式中，第二模式可循环程序循环是可用于可编程机器上的维护程序的定时循环。 在每个定时周期到期时，循环提供用于操作第二组内部机器功能的参考信号。 这种定时操作优选地与第一模式功能交错。

公开(公告)号：US5008816A

公开(公告)日：1991-04-16

申请号：US117715

申请日：1987-11-06

Applicant: Richard G. Fogg, Jr. ,  John W. Irwin

Inventor： Richard G. Fogg, Jr. ,  John W. Irwin

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399

CPC classification number: G06F12/0284 ,  G09G5/36 ,  G09G5/363

Abstract: A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port. Still further, the invention includes a memory system having a first group of memory locations that store information in accordance with the first address range and a second group of memory locations. The two groups of memory locations are connected to a controller that provides write access to the first group of memory locations in a response to write commands having addresses within the first address range and, simultaneously writing each write command address in the second group of memory locations.