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8 条记录 (耗时 0.038 秒)

    Method of manufacturing flash memory device
    3.
    发明申请
    Method of manufacturing flash memory device 审中-公开
    制造闪存设备的方法

    公开(公告)号：US20070004141A1

    公开(公告)日：2007-01-04

    申请号：US11479285

    申请日：2006-06-30

    申请人： Nam Kim ,  Eun Choi ,  Sang Oh

    发明人： Nam Kim ,  Eun Choi ,  Sang Oh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L27/115 ,  H01L27/11521

    摘要： A method of manufacturing a flash memory device which can improve capacitance and can reduce the interference phenomenon. According to one embodiment, a method of manufacturing a flash memory device includes the steps of depositing a tunnel oxide layer over a semiconductor substrate having a isolation structure, depositing a conductive layers for a floating gate over the tunnel oxide layer, forming an oxide layer between the conductive layers for the floating gate, forming a recess pattern in the conductive layers for the floating gate, and depositing a dielectric layer and a conductive layer for a control gate, respectively.

    摘要翻译： 一种可以改善电容并可以减少干扰现象的闪速存储器件的制造方法。 根据一个实施例，一种制造闪速存储器件的方法包括以下步骤：在具有隔离结构的半导体衬底上沉积隧道氧化物层，在隧道氧化物层之上沉积用于浮置栅极的导电层，在隧道氧化物层之间形成氧化物层 用于浮置栅极的导电层，在用于浮置栅极的导电层中形成凹陷图案，以及分别为控制栅极沉积介电层和导电层。

    NAND flash memory device and method of manufacturing the same
    6.
    发明申请
    NAND flash memory device and method of manufacturing the same 审中-公开
    NAND闪存器件及其制造方法

    公开(公告)号：US20070004099A1

    公开(公告)日：2007-01-04

    申请号：US11477729

    申请日：2006-06-28

    申请人： Eun Choi ,  Nam Kim

    发明人： Eun Choi ,  Nam Kim

    IPC分类号： H01L21/8232 ,  H01L21/335

    CPC分类号： H01L29/42324 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/40114

    摘要： A method of manufacturing a non-volatile memory device includes forming a first conductive layer over a tunnel dielectric layer that is provided on a semiconductor substrate. A non-conductive layer is formed over the first conductive film. The non-conductive layer is etched to define a stack structure between first and second trenches, the stack structure including the first conductive layer and the non-conductive layer. A second conductive layer is formed over the stack structure and into the first and second trenches. An upper portion of the second conductive layer is etched to expose the non-conductive layer of the stack structure. The non-conductive layer of the stack structure is removed to form a three-dimensional (3-D) floating gate with an opening, the floating gate including the first and second conductive layers. A third conductive layer is provided within the 3-D floating gate via the opening of the 3-D floating gate to form a control gate.

    摘要翻译： 制造非易失性存储器件的方法包括在设置在半导体衬底上的隧道电介质层上形成第一导电层。 在第一导电膜上形成非导电层。 蚀刻非导电层以限定第一和第二沟槽之间的堆叠结构，所述堆叠结构包括第一导电层和非导电层。 第二导电层形成在堆叠结构上并且进入第一和第二沟槽中。 蚀刻第二导电层的上部以暴露堆叠结构的非导电层。 去除堆叠结构的非导电层以形成具有开口的三维（3-D）浮置栅极，浮置栅极包括第一和第二导电层。 第三导电层通过3-D浮动栅极的开口设置在3-D浮动栅极内，以形成控制栅极。

    Method and system for rendering graphic data based on network
    7.
    发明申请
    Method and system for rendering graphic data based on network 审中-公开
    基于网络渲染图形数据的方法和系统

    公开(公告)号：US20050060433A1

    公开(公告)日：2005-03-17

    申请号：US10664212

    申请日：2003-09-17

    申请人： Eun Choi

    发明人： Eun Choi

    IPC分类号： H04L29/06 ,  H04L29/08 ,  G06F15/16

    CPC分类号： H04L29/06 ,  H04L67/1002 ,  H04L67/28 ,  H04L67/2819 ,  H04L67/2823 ,  H04L67/2842 ,  H04L69/04 ,  H04L69/329

    摘要： An integrated graphic rendering system, which is connected to users via a network, is provided. The system includes source graphic data-handling agents, an integrated rendering management server, and rendering execution tools. The agent selectively extracts graphic data, transforms the data into a predetermined format, compresses the data and sends them to the server. The server has a 1:N signal connection with the agents, and collects and decompresses the graphic data. The tools have parallel signal connections with the server, and perform distributed rendering of the SGD under control of the server, create rendered data, and output the rendered data to the server. The server sends distributed rendering commands to the tools, monitors rendering execution status of the tools, and checks rendering errors.

    摘要翻译： 提供了通过网络连接到用户的集成图形呈现系统。 该系统包括源图形数据处理代理，集成呈现管理服务器和呈现执行工具。 代理选择性地提取图形数据，将数据转换成预定格式，压缩数据并将其发送到服务器。 服务器与代理商进行1：N信号连接，并收集和解压缩图形数据。 这些工具与服务器具有并行信号连接，并在服务器的控制下执行SGD的分布式呈现，创建渲染数据，并将呈现的数据输出到服务器。 服务器向工具发送分布式渲染命令，监视渲染工具的执行状态，并检查渲染错误。

    Gene controlling flowering time of plants and method for manipulating flowering time of plant using the same
    8.
    发明申请
    Gene controlling flowering time of plants and method for manipulating flowering time of plant using the same 有权
    基因控制植物的开花时间和使用该植物操作植物开花时间的方法

    公开(公告)号：US20050034194A1

    公开(公告)日：2005-02-10

    申请号：US10780703

    申请日：2004-02-19

    申请人： Jong Lee ,  Yun Kim ,  Eun Choi ,  So Yoo ,  Ji Ahn ,  Yang Choi

    发明人： Jong Lee ,  Yun Kim ,  Eun Choi ,  So Yoo ,  Ji Ahn ,  Yang Choi

    IPC分类号： A01H5/00 ,  C07K14/415 ,  C12N5/10 ,  C12N15/29 ,  C12N15/82

    CPC分类号： C12N15/827 ,  C07K14/415

    摘要： The present invention relates to a gene controlling the flowering time of plants, and a method for manipulating the flowering time of plants using the gene. More particularly, the present invention relates to a LOV1 gene controlling the flowering time of plants, which is isolated from Arabidopsis thaliana, and also to a method for either delaying the flowering time of plants by overexpressing the LOV1 gene in the plants, or inducing the early flowering of the plants by repressing the expression of the LOV1 gene in the plants.

    摘要翻译： 本发明涉及控制植物开花时间的基因，以及使用该基因操作植物开花时间的方法。 更具体地，本发明涉及控制从拟南芥分离的植物的开花时间的LOV1基因，还涉及通过在植物中过表达LOV1基因延迟植物的开花时间的方法，或诱导 通过抑制植物中LOV1基因的表达来早期开花植物。