公开(公告)号：US20020037608A1

公开(公告)日：2002-03-28

申请号：US09956575

申请日：2001-09-18

申请人： Kabushiki Kaisha Toshiba

发明人： Shigeru Kawanaka ,  Takashi Yamada

IPC分类号： H01L021/84

CPC分类号： H01L29/66772 ,  H01L29/78609 ,  H01L29/78615

摘要： A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

摘要翻译： 半导体器件包括具有第一绝缘体的半导体衬底和形成在第一绝缘体上的半导体沟道区，其中半导体沟道区包括至少两个具有第一导电类型的第一区域，第二导电类型区域与 所述第一导电类型，所述第二区域设置在所述两个第一区域之间，形成在所述第二区域上的第二绝缘体，形成在所述第二绝缘体上的栅电极，具有与所述第二区域相同的导电类型的第三区域， 第三区域与第二区域导电，形成在第三区域上的第三绝缘体，第三绝缘体的宽度窄于用于隔离半导体形成区域的隔离区域的宽度，以及与第二区域相同的导电类型的第四区域， 第三区域的第四区域与第三区域导电。

公开(公告)号：US20020020878A1

公开(公告)日：2002-02-21

申请号：US09902700

申请日：2001-07-12

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shigeru Kawanaka

IPC分类号： H01L021/00 ,  H01L027/01 ,  H01L031/0392

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H03K19/0948

摘要： A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

摘要翻译： 安装在半导体集成电路上的多输入逻辑电路（例如，2输入NAND电路）包括多个具有相同沟道导通类型并且在电源端子和输出端子之间串联电连接的电压激活晶体管 。 至少连接到输出端子的电压激活晶体管的源极区域和主体区域电连接并且具有基本上相同的电位。 半导体集成电路具有SOI或SOS结构。

公开(公告)号：US20020127784A1

公开(公告)日：2002-09-12

申请号：US10128004

申请日：2002-04-22

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shigeru Kawanaka ,  Takashi Yamada

IPC分类号： H01L021/00

CPC分类号： H01L29/66772 ,  H01L29/78609 ,  H01L29/78615

摘要： A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

公开(公告)号：US20020098643A1

公开(公告)日：2002-07-25

申请号：US10107657

申请日：2002-03-25

申请人： Kabushiki Kaisha Toshiba

发明人： Shigeru Kawanaka ,  Takashi Yamada

IPC分类号： H01L021/8242

CPC分类号： H01L29/66772 ,  H01L29/78609 ,  H01L29/78615

摘要： A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

公开(公告)号：US20020140115A1

公开(公告)日：2002-10-03

申请号：US10106371

申请日：2002-03-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kazumi Inoh ,  Shigeru Kawanaka ,  Yoshihiro Minami ,  Yasuhiro Katsumata

IPC分类号： H01L023/544

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.

摘要翻译： 半导体器件包括：半导体衬底; 设置在所述半导体衬底上的绝缘层; 设置在所述绝缘层上的第一半导体层; 穿过所述第一半导体层和所述绝缘层并到达所述半导体衬底的多个开口; 以及通过选择性生长填充所述开口并连接到所述半导体衬底的第二半导体层，其中所述多个开口的面尺寸基本相等。

公开(公告)号：US20030205760A1

公开(公告)日：2003-11-06

申请号：US10439370

申请日：2003-05-16

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shigeru Kawanaka ,  Takashi Yamada

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/66772 ,  H01L29/78609 ,  H01L29/78615

摘要： A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

公开(公告)号：US20030162356A1

公开(公告)日：2003-08-28

申请号：US10400566

申请日：2003-03-28

申请人： Kabushiki Kaisha Toshiba

发明人： Shigeru Kawanaka

IPC分类号： H01L021/8234 ,  H01L021/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H03K19/0948

摘要： A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

摘要翻译： 安装在半导体集成电路上的多输入逻辑电路（例如，2输入NAND电路）包括多个具有相同沟道导通型的电压激活晶体管，并串联电连接在电源端子和输出端 终奌站。 至少连接到输出端子的电压激活晶体管的源极区域和体区域电连接并且具有基本上相同的电位。 半导体集成电路具有SOI或SOS结构。

公开(公告)号：US20030111681A1

公开(公告)日：2003-06-19

申请号：US10075464

申请日：2002-02-15

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shigeru Kawanaka

IPC分类号： H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119 ,  H01L027/01 ,  H01L027/11

CPC分类号： H01L21/84 ,  G11C11/405 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/7841

摘要： According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.

摘要翻译： 根据本发明的一个方面，半导体存储器件具有：形成在绝缘膜上的半导体层; 以及包括由串联连接的第一和第二晶体管构成的多个存储单元的矩阵排列的存储单元阵列，每个存储单元的一侧连接到位线，并且每个存储单元的另一侧被提供 参考电位，并且根据本发明的另一方面，半导体存储器件制造方法包括：在半导体衬底上形成氧化物层和硅有源层; 形成用于将所述硅有源层分离成离散元件形成区域以与所述硅有源层基本齐平的元件隔离区; 通过在所述硅有源层上沉积栅极材料并对其进行构图来形成成对的两个晶体管的栅电极; 将所述栅极用作离子注入掩模，将预定离子注入用于形成扩散层的区域中; 通过热过程激活注入的离子来形成所述成对晶体管; 以及形成连接到所述成对晶体管之一的栅极的第一栅极线和连接到所述成对晶体管中另一个的栅电极的第二栅极线。