公开(公告)号：US20180308933A1

公开(公告)日：2018-10-25

申请号：US16022737

申请日：2018-06-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Cheng Tung

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/02634 ,  H01L21/3085 ,  H01L21/76278 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.

公开(公告)号：US07071039B2

公开(公告)日：2006-07-04

申请号：US10360741

申请日：2003-02-10

申请人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Osamu Fujii

发明人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Osamu Fujii

IPC分类号： H01L21/00

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203

摘要： A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.

公开(公告)号：US06908833B1

公开(公告)日：2005-06-21

申请号：US10366773

申请日：2003-02-14

申请人： Kamesh Gadepally

发明人： Kamesh Gadepally

IPC分类号： H01L21/203 ,  H01L21/363 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76278 ,  H01L29/78

摘要： A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.

摘要翻译： 一种用于形成电气装置的工艺和结构。 该方法和结构提供在基底上形成绝缘层。 然后通过将硅原子注入到绝缘层中而在绝缘层中形成导电区域。 此外，可以在绝缘层中形成多个不同的导电区域。 然后可以在每个导电区域中形成诸如晶体管或二极管的电气装置。 因为导电区域形成在与其它导电区域很大程度上电隔离的导电区域中，相邻的器件几乎不会引起干扰。

公开(公告)号：US06727567B2

公开(公告)日：2004-04-27

申请号：US10091291

申请日：2002-03-05

申请人： John Joseph Bastek ,  Thomas J. Krutsick ,  Robert D. Plummer

发明人： John Joseph Bastek ,  Thomas J. Krutsick ,  Robert D. Plummer

IPC分类号： H01L2900

CPC分类号： H01L29/66272 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L27/0207

摘要： Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.

摘要翻译： 使用选择性外延生长（SEG）在衬底晶片中形成集成电路器件。 当跨越晶片表面的SEG区域的分布不均匀时，产生不均匀的外延晶片厚度，导致在生长过程中的负载效应。 根据本发明，加载效应被最小化，通过添加无源SEG区域，从而在晶片上产生相对均匀的SEG生长区域分布。 无源区域在成品IC器件中保持未处理。

公开(公告)号：US06558994B2

公开(公告)日：2003-05-06

申请号：US09841564

申请日：2001-03-01

申请人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S438/967 ,  H01L2924/00

摘要： A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

公开(公告)号：US20020140115A1

公开(公告)日：2002-10-03

申请号：US10106371

申请日：2002-03-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kazumi Inoh ,  Shigeru Kawanaka ,  Yoshihiro Minami ,  Yasuhiro Katsumata

IPC分类号： H01L023/544

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.

摘要翻译： 半导体器件包括：半导体衬底; 设置在所述半导体衬底上的绝缘层; 设置在所述绝缘层上的第一半导体层; 穿过所述第一半导体层和所述绝缘层并到达所述半导体衬底的多个开口; 以及通过选择性生长填充所述开口并连接到所述半导体衬底的第二半导体层，其中所述多个开口的面尺寸基本相等。

公开(公告)号：US20020019083A1

公开(公告)日：2002-02-14

申请号：US09915753

申请日：2001-07-26

申请人： STMicroelectronics S.A.

发明人： Herve Jaouen ,  Vincent Le Goascoz

IPC分类号： H01L021/84 ,  H01L021/00 ,  H01L021/331 ,  H01L021/8222

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76278

摘要： A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.

摘要翻译： 从具有两个平行主表面的第一半导体衬底制造包括由绝缘材料包围并放置在另一绝缘材料上的半导体材料的胰岛的系统的方法包括形成第一绝缘材料层，并在 第一半导体衬底的顶部主表面是形成半导体材料的小岛的薄的半导体层。 可以相对于第一半导体衬底选择性地蚀刻薄半导体层。 在半导体材料的胰岛和薄半导体层的暴露表面上形成第二绝缘材料层。 该方法还包括移除第一半导体衬底。

公开(公告)号：US6057214A

公开(公告)日：2000-05-02

申请号：US987408

申请日：1997-12-09

申请人： Keith A. Joyner

发明人： Keith A. Joyner

IPC分类号： H01L21/762 ,  H01L21/36

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L21/76283

摘要： A silicon-on-insulator trench isolation structure is disclosed that includes an active silicon-on-insulator region, an active bulk substrate region, and a trench region positioned between the active silicon-on-insulator region and the active bulk substrate region. The active silicon-on-insulator region is provided with a silicon-on-insulator film (42) positioned above a buried insulator layer (32). The active bulk substrate region may be provided between two trench regions such as a trench region (20) and a trench region (22). The trench region (20) is positioned between the active silicon-on-insulator region and the active bulk substrate region.

摘要翻译： 公开了一种绝缘体上硅沟槽隔离结构，其包括绝缘体上活性区域，活性体基板区域和位于有源绝缘体上的硅区域和活性体基板区域之间的沟槽区域。 有源绝缘体上的区域设置有位于掩埋绝缘体层（32）上方的绝缘体上硅膜（42）。 活性体基板区域可以设置在诸如沟槽区域（20）和沟槽区域（22）的两个沟槽区域之间。 沟槽区域（20）位于有源绝缘体上的区域和活性体基底区域之间。

公开(公告)号：US4507158A

公开(公告)日：1985-03-26

申请号：US522767

申请日：1983-08-12

申请人： Theodore I. Kamins ,  Donald R. Bradbury ,  Clifford I. Drowley

发明人： Theodore I. Kamins ,  Donald R. Bradbury ,  Clifford I. Drowley

IPC分类号： H01L27/08 ,  H01L21/20 ,  H01L21/205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L29/786 ,  H01L21/95

CPC分类号： H01L21/76 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76278 ,  H01L21/76283 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/085

摘要： A method for trench isolation of a silicon island for device fabrication using only conventional very large scale integration (VLSI) techniques is provided. The combination of the sidewall isolation achieved with the trench isolation and the underlying oxide film create a totally dielectrically isolated structure without the possibility of latch-up between adjacent devices.

摘要翻译： 提供了用于仅使用传统的大规模集成（VLSI）技术的用于器件制造的硅岛的沟槽隔离的方法。 通过沟槽隔离和下面的氧化膜实现的侧壁隔离的组合产生完全介电隔离的结构，而不会在相邻器件之间产生闩锁。

公开(公告)号：US20160218177A1

公开(公告)日：2016-07-28

申请号：US15090000

申请日：2016-04-04

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/7851

摘要： An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

摘要翻译： 可以通过在单晶硅基衬底的隔离凹槽中形成掩埋隔离层来形成集成电路。 在掩埋隔离层处的衬底的暴露的侧表面被电介质侧壁覆盖。 通过掩埋隔离层形成晶种沟以暴露衬底。 通过种子沟槽形成单晶硅基种子层，在掩埋隔离层的顶表面上方延伸。 形成接触种子层的硅基非晶层。 在非晶层上形成覆盖层。 辐射诱导的再结晶过程将非晶层转化成与种子层对准的单晶层。 盖层被去除并且单晶层被平坦化，在掩埋隔离层上留下隔离的半导体层。