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    Thin film transistor with multiple gates using metal induced lateral crystalization and method of fabricating the same
    3.
    发明申请
    Thin film transistor with multiple gates using metal induced lateral crystalization and method of fabricating the same 有权
    使用金属诱导横向晶化的具有多个栅极的薄膜晶体管及其制造方法

    公开(公告)号：US20040253772A1

    公开(公告)日：2004-12-16

    申请号：US10890999

    申请日：2004-07-15

    申请人： Samsung SDI Co., Ltd.

    发明人： Woo-Young So

    IPC分类号： H01L021/84

    CPC分类号： H01L29/78696 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/6675 ,  H01L29/78609 ,  H01L29/78645

    摘要： A thin film transistor with multiple gates using an MILC process which is capable of materializing multiple gates without increasing dimensions and a method thereof. The thin film transistor has a semiconductor layer which is formed on a insulating substrate in a zigzag shape; and a gate electrode which is equipped with one or more slots intersecting with the semiconductor layer, the semiconductor layer includes two or more body parts intersecting with the gate electrode; and one or more connection parts connecting each neighboring body part, wherein a part overlapping the semiconductor layer in the gate electrode acts as a multiple gate, and MILC surfaces are formed at a part which does not intersect with the gate electrode in the semiconductor layer.

    摘要翻译： 一种具有使用MILC工艺的多个栅极的薄膜晶体管，其能够实现多个栅极而不增加其尺寸及其方法。 薄膜晶体管具有以Z字形形成在绝缘基板上的半导体层; 以及配置有与所述半导体层交叉的一个以上的槽的栅电极，所述半导体层包括与所述栅电极交叉的两个以上的主体部; 以及一个或多个连接每个相邻主体部分的连接部分，其中与栅电极中的半导体层重叠的部分用作多栅极，并且MILC表面形成在半导体层中不与栅电极不相交的部分。

    METHOD OF FORMING A THIN FILM TRANSISTOR BY UTILIZING A LASER CRYSTALLIZATION PROCESS
    4.
    发明申请
    METHOD OF FORMING A THIN FILM TRANSISTOR BY UTILIZING A LASER CRYSTALLIZATION PROCESS 失效
    利用激光结晶过程形成薄膜晶体管的方法

    公开(公告)号：US20040250754A1

    公开(公告)日：2004-12-16

    申请号：US10709980

    申请日：2004-06-10

    发明人： Ching-Wei Lin

    IPC分类号： C30B023/00 ,  C30B025/00 ,  C30B028/12 ,  H01L021/00 ,  C30B028/14 ,  H01L021/84

    CPC分类号： H01L21/02683 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02686 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/66787 ,  H01L29/78675 ,  H01L29/78696

    摘要： An amorphous silicon pattern is formed first. A first region, a second region, at least one first pointed region adjacent to the second region and having a second height, at least one fourth region between the first region and each first pointed region are included in the amorphous silicon pattern. Each fourth region has a fourth height smaller than the second height. A laser crystallization process is performed to form a first single crystal silicon grain in each fourth region.

    摘要翻译： 首先形成非晶硅图案。 第一区域，第二区域，与第二区域相邻并具有第二高度的至少一个第一尖锐区域，第一区域和第一尖锐区域之间的至少一个第四区域包括在非晶硅图案中。 每个第四区域具有比第二高度小的第四高度。 执行激光结晶处理以在每个第四区域中形成第一单晶硅晶粒。

    Method of forming a CMOS thin film transistor device
    5.
    发明申请
    Method of forming a CMOS thin film transistor device 有权
    形成CMOS薄膜晶体管器件的方法

    公开(公告)号：US20040241919A1

    公开(公告)日：2004-12-02

    申请号：US10630196

    申请日：2003-07-29

    发明人： Chih-Chin Chang ,  Chih-Hung Wu

    IPC分类号： H01L021/00 ,  H01L021/84

    CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/127

    摘要： A method of forming a CMOS thin film transistor device. A dry etching procedure is performed to remove part of a photoresist layer and part of a metal layer and thus forms a gate with a symmetrical cone shape and a remaining photoresist layer. The dielectric layer is thus exposed in the lightly doped area. Specially, the bottom width of the first gate is narrower than that of the first metal layer and the symmetrical cone shape is gradually thinner from bottom to top. Using the gate as a mask, an nnull-ion implantation is performed to form a self-aligned and symmetrical LDD region in a semiconductor layer without additional photolithography steps.

    摘要翻译： 一种形成CMOS薄膜晶体管器件的方法。 执行干蚀刻步骤以去除部分光致抗蚀剂层和金属层的一部分，从而形成具有对称锥形形状的栅极和剩余的光致抗蚀剂层。 因此，电介质层暴露在轻掺杂区域中。 特别地，第一栅极的底部宽度比第一栅极的底部宽度窄，并且对称的锥形形状从底部到顶部逐渐变薄。 使用栅极作为掩模，进行n - 离子注入以在半导体层中形成自对准和对称的LDD区域，而无需额外的光刻步骤。

    Lamination and delamination technique for thin film processing
    7.
    发明申请
    Lamination and delamination technique for thin film processing 审中-公开

    公开(公告)号：US20040235267A1

    公开(公告)日：2004-11-25

    申请号：US10444395

    申请日：2003-05-23

    发明人： James Sheats ,  Tue Nguyen

    IPC分类号： H01L021/44 ,  H01L021/00 ,  H01L021/84 ,  H01L021/30

    CPC分类号： H01L21/6835 ,  H01L21/67092 ,  H01L21/67132 ,  H01L29/66757 ,  H01L29/66765 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/19041 ,  H05K3/046

    摘要： This invention discloses a releasable adhesion layer having good adhesion during high temperature fabrication process in the absence of light, and delaminating at a lower temperature in the presence of light. One embodiment of this invention is a film of polymer whose thermal decomposition temperature changes drastically upon photoexposure. These materials, prior to photoexposure, can withstand temperatures in the range of approximately 200null C. to 300null C. without decomposition, yet decompose at around 100null C. with photoexposure. The releasable adhesion layer can be used in a thermal transfer element, sandwiching a donor substrate and a transfer layer having a plurality of multicomponent transfer units. In the absence of light, the releasable adhesion layer can sustain high temperature processing of these multicomponent transfer units. By photoexposing according to a pattern, the photoexposed multicomponent transfer units can be selectively released at a low temperature to transfer to a receptor.

    Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor
    8.
    发明申请
    Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor 失效
    用于形成SOI衬底，垂直晶体管和具有垂直晶体管的存储单元的方法

    公开(公告)号：US20040197965A1

    公开(公告)日：2004-10-07

    申请号：US10792691

    申请日：2004-03-05

    发明人： Albert Birner ,  Steffen Breuer ,  Matthias Goldbach ,  Joern Luetzen ,  Dirk Schumann

    IPC分类号： H01L021/00 ,  H01L021/8242 ,  H01L021/84

    CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

    摘要： A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.

    摘要翻译： 在任何期望的几何形状的硅表面上制造绝缘体上硅层结构的方法可以局部地产生绝缘体上硅结构。 该方法包括在硅表面区域形成中孔，中孔表面的氧化形成硅单晶的硅氧化物和肋状区域; 以及执行选择性外延工艺，其中硅在相对于氧化硅区域选择性地在未覆盖的肋区域上生长。 肋区域保持在相邻的中孔之间的适当位置，一旦达到肋区域的预定的最小硅壁厚度，则该步骤结束，肋区域的露出，其布置在远离半导体衬底的相邻介孔之间的端部 。 该方法可用于制造具有这种类型的选择晶体管的垂直晶体管和存储单元。

    Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit
    9.
    发明申请
    Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit 有权
    制造半导体集成电路和半导体集成电路的方法

    公开(公告)号：US20040191967A1

    公开(公告)日：2004-09-30

    申请号：US10766587

    申请日：2004-01-28

    申请人： SEIKO INSTRUMENTS INC.

    发明人： Miwa Wake ,  Yoshifumi Yoshida

    IPC分类号： H01L021/00 ,  H01L021/84

    CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624

    摘要： Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation. A method of the present invention includes the steps of: forming and patterning a LOCOS reaching an embedded insulating film, a gate oxide film, a well and a polysilicon film serving as a gate electrode; forming a second conductivity type high-density impurity region in an ultra-shallow portion of each of a source region and a drain region, a second conductivity type impurity region having a low density under the second conductivity type high-density impurity region of the ultra-shallow portion, and a second conductivity type impurity region having a high density under the second conductivity type impurity region having a low density and above the embedded insulating film; forming a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region and the gate electrode; and forming a wiring on the interlayer insulating film.

    摘要翻译： 通常，当支撑基板的电位固定时，产生如下问题：即使在使用支撑基板的寄生晶体管的产生时，即使在漏极附近的嵌入绝缘膜附近也产生冲击离子，作为 门，以便可能引起寄生双极性操作。 本发明的方法包括以下步骤：形成和图案化到达嵌入式绝缘膜的LOCOS，栅极氧化膜，阱和用作栅电极的多晶硅膜; 在源极区域和漏极区域的每一个的超浅部分中形成第二导电型高密度杂质区域，在超导体的第二导电型高密度杂质区域处具有低密度的第二导电类型杂质区域 在第二导电型杂质区具有低密度且高于嵌入绝缘膜的第二导电型杂质区; 在所述栅电极周围形成侧壁; 在源极区域和漏极区域中形成第二导电型杂质区域; 形成层间绝缘膜，并在源极区，漏极区和栅电极中形成接触孔; 并在层间绝缘膜上形成布线。