公开(公告)号：US20230017909A1

公开(公告)日：2023-01-19

申请号：US17681547

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Daisuke FUJIWARA ,  Toshio FUJISAWA

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

公开(公告)号：US20220083261A1

公开(公告)日：2022-03-17

申请号：US17335511

申请日：2021-06-01

Applicant: Kioxia Corporation

Inventor： Daisuke FUJIWARA ,  Tomoya SANUKI ,  Toshio FUJISAWA

IPC: G06F3/06

Abstract: A memory system of an embodiment includes a NAND memory and a memory controller. The NAND memory includes an encoder configured to convert first data into second data including a plurality of code words generated by dividing the first data into the code words, generate parity data in a horizontal direction of the second data for error check and correct for each code word and encode the first data, and a decoder. A control circuit of the NAND memory controls the decoder to perform hard decision decoding using the parity data in the horizontal direction on readout target data when a readout command is received and outputs the decoded readout target data to the memory controller when the hard decision decoding of the readout target data is successful.