公开(公告)号：US12125542B2

公开(公告)日：2024-10-22

申请号：US17695529

申请日：2022-03-15

Applicant: KIOXIA CORPORATION

Inventor： Wataru Moriyama ,  Hayato Konno ,  Takao Nakajima ,  Fumihiro Kono ,  Masaki Fujiu ,  Kiyoaki Iwasa ,  Tadashi Someya

IPC: G11C16/04 ,  G11C16/16 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

公开(公告)号：US11917826B2

公开(公告)日：2024-02-27

申请号：US17868315

申请日：2022-07-19

Applicant: Kioxia Corporation

Inventor： Fumihiro Kono

IPC: G11C16/04 ,  H10B43/27 ,  G11C16/26 ,  H10B41/20 ,  H10B43/30 ,  G11C5/02 ,  H01L23/498 ,  H10B43/20

CPC classification number: H10B43/27 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/26 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H10B41/20 ,  H10B43/30 ,  G11C2213/71 ,  H10B43/20

Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

公开(公告)号：US11430805B2

公开(公告)日：2022-08-30

申请号：US16852990

申请日：2020-04-20

Applicant: Kioxia Corporation

Inventor： Fumihiro Kono

IPC: G11C16/04 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/11551 ,  G11C5/02 ,  H01L27/11568 ,  H01L23/498 ,  H01L27/11578

Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.