公开(公告)号：US11011211B2

公开(公告)日：2021-05-18

申请号：US16804956

申请日：2020-02-28

Applicant: KIOXIA CORPORATION

Inventor： Hiromitsu Komai

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/409

Abstract: A semiconductor storage device includes a plurality of memory cells and a plurality of bit lines connected thereto, a plurality of sense amplifier units respectively connected to the plurality of bit lines, and a cache memory connected to the plurality of sense amplifier units. Each sense amplifier unit includes a sense node and a latch in which data transferred onto the sense node from a corresponding bit line is latched. First data latched in a first sense amplifier unit among the plurality of sense amplifier units is transferred to the cache memory, and second data latched in a second sense amplifier unit among the plurality of sense amplifier units is transferred to the sense node of the first second sense amplifier unit. Thereafter, the second data is latched in the first sense amplifier unit and transferred to the cache memory.

公开(公告)号：US11894095B2

公开(公告)日：2024-02-06

申请号：US17685230

申请日：2022-03-02

Applicant: KIOXIA CORPORATION

Inventor： Yuji Satoh ,  Hiromitsu Komai

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1087

Abstract: A semiconductor memory device includes a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit, and a data bus that is connected to the plurality of data latch circuits. Each of the data latch circuits includes an inverter circuit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and at least three MOS transistors between the inverter circuit and the data bus. The at least three MOS transistors may be multiple N-channel type MOS transistors and at least one P-channel type MOS transistor connected in parallel between the inverter circuit and the data bus, or at least one N-channel type MOS transistor and multiple P-channel type MOS transistors connected in parallel between the inverter circuit and the data bus.

公开(公告)号：US11417401B2

公开(公告)日：2022-08-16

申请号：US17008209

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Mario Sako ,  Hiromitsu Komai ,  Masahiro Yoshihara

IPC: G11C16/26 ,  H01L23/522 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556

Abstract: A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.